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| motorola.com/semiconductors m68hc11 microcontrollers mc68hc711d3/d rev. 2 mc68hc711d3 data sheet 9/2003 mc68hc11d3 mc68hc11d0 mc68l11d0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola 3 motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2003 mc68hc711d3 data sheet to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history data sheet mc68hc711d3 ? rev. 2 4 revision history motorola revision history date revision level description page number(s) september, 2003 2 reformatted to curent publications standards n/a removed references to prog mode. throughout corrected pin assignments for: figure 1-2. pin assignments for 40-pin plastic dip figure 1-3. pin assignments for 44-pin plcc added figure 1-4. pin assign ments for 44-pin qfp 15 15 16 1.9 interrupt request (irq) ? reworked description for clarity. 18 2.4 programmable read-only memory (prom) ? updated with additional data. 31 section 10. ordering informatio n and mechanical specifications ? added mechanical specifications for 44-pin plastic quad flat pack (qfp). 133 added the following appendices: appendix a. mc68hc11d3 and mc68hc11d0 appendix b. mc68l11d0 137 143 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola list of sections 5 data sheet ? mc68hc711d3 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 section 2. operating modes and memory . . . . . . . . . . . . . . . . . . . . . . 21 section 3. central processor un it (cpu) . . . . . . . . . . . . . . . . . . . . . . . 35 section 4. resets, interr upts, and low-power modes . . . . . . . . . . . . 51 section 5. input/output (i/o) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 6. serial communications interface (sci). . . . . . . . . . . . . . . . 73 section 7. serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . 87 section 8. programmable timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 section 9. electrical character istics . . . . . . . . . . . . . . . . . . . . . . . . . . 117 section 10. ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 appendix a. mc68hc11d3 and mc68hc11d0. . . . . . . . . . . . . . . . . . 137 appendix b. mc68l11d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections data sheet mc68hc711d3 ? rev. 2 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola table of contents 7 data sheet ? mc68hc711d3 table of contents section 1. gener al description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5 power supply (v dd , v ss , and ev ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 reset (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.7 crystal driver and external clock input (xtal and extal) . . . . . . . . . 17 1.8 e-clock output (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.9 interrupt request (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.10 non-maskable interrupt/programming voltage (xirq /v pp ) . . . . . . . . . . 18 1.11 moda and modb (moda/lir and modb/v stby ) . . . . . . . . . . . . . . . . 18 1.12 read/write (r/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.13 port d bit 6/address strobe (pd6/as) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.14 input/output lines (pa7?pa0, pb7?pb0, pc7?pc0, and pd7?pd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 section 2. operati ng modes and memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 expanded multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3 special bootstrap mode (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.4 special test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.1 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.2 ram and i/o mapping register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.3 configuration control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4 programmable read-only memory (prom) . . . . . . . . . . . . . . . . . . . . . 31 2.4.1 programming an individual eprom address. . . . . . . . . . . . . . . . . . 32 2.4.2 programming the eprom with downloaded data . . . . . . . . . . . . . . 32 2.4.3 prom programming control register . . . . . . . . . . . . . . . . . . . . . . . 33 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc711d3 ? rev. 2 8 table of contents motorola section 3. central processor un it (cpu) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.1 accumulators a, b, and d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.2 index register x (ix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.3 index register y (iy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.6.1 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.6.2 overflow (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.6.3 zero (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.6.4 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.6.5 i-interrupt mask (i). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.6.6 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.6.7 x-interrupt mask (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.6.8 stop disable (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.3 extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.4 indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.5 inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.6 relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 section 4. resets, interr upts, and low-power modes 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.1 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.2 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.3 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . 52 4.2.4 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.5 system configuration options register . . . . . . . . . . . . . . . . . . . . . . 53 4.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.3.1 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.2 illegal opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.3 real-time interrupt (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.4 interrupt mask bits in the ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.5 priority structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.6 highest priority i interrupt and miscellaneous register (hprio). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc711d3 ? rev. 2 data sheet motorola table of contents 9 4.4 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.2 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 section 5. input/o utput (i/o) ports 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.1 port b data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.2 port b data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4.1 port c control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4.2 port c data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4.3 port c data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.1 port d data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.2 port d data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 section 6. serial comm unications interface (sci) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 wakeup feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.1 idle-line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.2 address-mark wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.6 sci error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.7 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.7.1 sci data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.7.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.7.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.7.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.7.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8 status flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 7. serial peri pheral interface (spi) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3 spi transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc711d3 ? rev. 2 10 table of contents motorola 7.5 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.1 master in/slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.2 master out/slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.6 spi system errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.7 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.7.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.7.2 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.7.3 spi data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 section 8. prog rammable timer 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.2 timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.3.1 timer control 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.2 timer input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.3 timer input capture 4/output compare 5 register . . . . . . . . . . . . 101 8.4 output compare (oc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.1 timer output compare registers. . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4.3 output compare 1 mask register . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.4 output compare 1 data register . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.5 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.6 timer control 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.7 timer interrupt mask 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.4.8 timer interrupt flag 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.9 timer interrupt mask 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.10 timer interrupt flag 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5 real-time interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.1 timer interrupt mask 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.2 timer interrupt flag 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5.3 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . . . . 112 8.6 computer operating properly watchdog function. . . . . . . . . . . . . . . . 113 8.7 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.7.1 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.2 pulse accumulator count register. . . . . . . . . . . . . . . . . . . . . . . . . 115 8.7.3 pulse accumulator status and interrupt bits . . . . . . . . . . . . . . . . . 115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc711d3 ? rev. 2 data sheet motorola table of contents 11 section 9. electri cal characteristics 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3 functional operating temperature range . . . . . . . . . . . . . . . . . . . . . . 118 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.7 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.8 expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.9 serial peripheral interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 section 10. ordering informat ion and mechanical specifications 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.3 40-pin dip (case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.4 44-pin plcc (case 777-02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.5 44-pin qfp (case 824a-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 appendix a. mc68hc11d 3 and mc68hc11d0 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 a.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 a.3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 a.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 a.5 mc68hc11d3 and mc68hc11d0 electrical characteristics. . . . . . . . 140 a.5.1 functional operating temperature range . . . . . . . . . . . . . . . . . . . 140 a.5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 a.6 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 appendix b. mc68l11d0 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 b.2 mc68l11d0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 143 b.2.1 functional operating temperature range . . . . . . . . . . . . . . . . . . . 143 b.2.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 b.2.3 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 b.2.4 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 b.2.5 expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 b.2.6 serial peripheral interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 147 b.3 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc711d3 ? rev. 2 12 table of contents motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola general description 13 data sheet ? mc68hc711d3 section 1. general description 1.1 introduction this section depicts the general characteri stics and features of the mc68hc711d3 high-density complementary metal-oxide semiconductor (hcmos) microcontroller unit (mcu). the mc68hc711d3 contains highly soph isticated on-chip peripheral functions. this high-speed, low-power programmabl e read-only memory (prom) mcu has a nominal bus speed of 3 mhz. the full y static design allows operations at frequencies down to dc. the mc68hc11d3 and mc68hc11d0 ar e read-only memory (rom) based high-performance microcontrollers (mcu) based on the mc68hc11e9 design. the mc68l11d0 is an extended-voltage version of the mc68hc11d0 that can operate in applications that require supply voltages as low as 3.0 v. the information in this document pertains to al l the devices with the exceptions noted in appendix a. mc68hc11d3 and mc68hc11d0 and appendix b. mc68l11d0 . 1.2 features features of the mc68hc711d3 include: expanded 16-bit timer system with four-stage programmable prescaler non-return-to-zero (nrz) serial communications interface (sci) power-saving stop and wait modes 64 kbytes memory addressability multiplexed address/data bus serial peripheral interface (spi) 4 kbytes of one-time programmable read-only memory (otprom) 8-bit pulse accumulator circuit 192 bytes of static random-access memory (ram) (all saved during standby) real-time interrupt (rti) circuit computer operating properly (cop) watchdog system f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc711d3 ? rev. 2 14 general description motorola available in these packages: ? 40-pin plastic dual in-line package (dip) ? 44-pin plastic leaded chip carrier (plcc) ? 44-pin plastic quad flat pack (qfp) 1.3 structure refer to figure 1-1 , which shows the structure of the mc68hc711d3 mcu. figure 1-1. mc68hc711d3 block diagram port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 mode control interrupt control moda/lir modb/v stby reset irq xirq /v pp xtal extal e clock logic oscillator pai/oc1 oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5/oc1 ic1 ic2 ic3 timer pulse accumulator cop periodic interrupt 4 kbytes pd7/r/w pd6/as pd5 pd4 pd3 pd2 pd1 pd0 data direction register d port d data direction register c port c data direction register b port b pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 multiplexed address/data bus 192 bytes static ram serial peripheral interface (spi) serial communications interface (sci) mc68hc711d3 cpu core ss sck mosi miso txd rxd v ss v dd ev ss eprom or otprom not bonded in 40-pin package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin descriptions mc68hc711d3 ? rev. 2 data sheet motorola general description 15 1.4 pin descriptions refer to figure 1-2 , figure 1-3 , and figure 1-4 for pin assignments. figure 1-2. pin assignments for 40-pin plastic dip figure 1-3. pin assignments for 44-pin plcc pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa5 pa7 v dd pb4 pb3 pb2 pb1 pb0 modb/v stby moda/lir e extal xtal pc7 xirq /v pp pd7/r/w pd6/as reset irq pd0 pd1 pd2 pd3 pd4 pd5 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v ss 9 10 11 12 13 14 15 16 17 18 19 20 8 7 6 5 4 3 2 1 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 pc4 pc5 pc6 pc7 xirq /v pp pd7/r/w pd6/as reset irq pd0 pd1 pb2 pb3 pb4 pb5 pb6 pb7 nc pa0 pa1 pc3 pc2 pd1 pc0 v ss ev ss xtal extal e moda/lir modb/v stby pd2 pd3 pd4 pd5 v dd pa7 pa6 pa5 pa4 pa3 pa2 7 8 9 10 11 12 13 14 15 16 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 17 pb1 38 pb0 39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc711d3 ? rev. 2 16 general description motorola figure 1-4. pin assignments for 44-pin qfp 1.5 power supply (v dd , v ss , and ev ss ) power is supplied to the mcu through v dd and v ss . v dd is the power supply (+5 v 10%) and v ss is ground (0 v). ev ss , available on the 44-pin plcc and qfp, is an additional ground pin. 1.6 reset (reset ) an active low bidirecti onal control signal, reset , acts as an input to initialize the mcu to a known startup state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (cop) watchdog circuit. in addition, the state of this pin is one of the factors governing the selection of boot mode. pc4 pc5 pc6 pc7 xirq pd7 pd6 reset irq pd0 pd1 pb2 pb3 pb4 pb5 pb6 pb7 nc pa0 pa1 pc3 pc2 pc1 pc0 ev ss v ss xtal extal e moda modb pd2 pd3 pd4 pd5 v dd pa7 pa6 pa5 pa4 pa3 pa2 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 43 42 41 40 39 38 37 36 35 34 pb1 32 pb0 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description crystal driver and external clock input (xtal and extal) mc68hc711d3 ? rev. 2 data sheet motorola general description 17 1.7 crystal driver and external clock input (xtal and extal) these two pins provide the interface for either a crystal or a cmos compatible clock to control the internal clock gener ator circuitry. the frequency applied to these pins is four times higher than the desired e-clock rate. refer to figure 1-5 for crystal and clock connections. figure 1-5. oscillator connections 10 m * values includes all stray capacitances. first mcu extal xtal 4 x e crystal mcu extal xtal 4 x e cmos-compatible external oscillator nc or 10k?100k load 25 pf * 25 pf * second mcu extal xtal nc or 10k?100k load 10 m mcu extal xtal 4 x e crystal 25 pf * 25 pf * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc711d3 ? rev. 2 18 general description motorola 1.8 e-clock output (e) e is the output connection for the inter nally generated e clock. the signal from e is used as a timing reference. the frequency of the e-clock output is one fourth that of the input frequency at the xtal and extal pins. the e clock can be turned off in single-chip mode for greater noise immunity if desired. see 4.3.6 highest priority i interrupt and miscellaneous register (hprio) for details. 1.9 interrupt request (irq ) the irq input provides a means of applying asynchronous interrupt requests to the microcontroller unit (mcu). either negative edge-sensitive triggering or level-sensitive triggering is program selectable by using the irqe bit of the option register. irq is always configured to level-sensitive triggering at reset. while the programmable read-only memory (prom) is being programmed, this pin provides the chip enable (ce ) signal. to prevent accidental programming of the prom during reset, an external resistor is required on irq to pull the pin to v dd . 1.10 non-maskable interrupt/p rogramming voltage (xirq /v pp ) the xirq input provides the capability for asynchronously applying non-maskable interrupts to the mcu after a power-on reset (por). during reset, the x bit in the condition code register (ccr) is set ma sking any interrupt until enabled by software. this level-sensitive input requ ires an external pullup resistor to v dd . in the programming configuration of the boot strap mode, this pin is used to supply one-time programmable read-only memo ry (otprom) programming voltage, v pp , to the mcu. to avoid programming accid ents during reset, this pin should be equal to v dd during normal operation unless xirq is active. 1.11 moda and modb (moda/lir and modb/v stby ) as reset transitions, these pins are used to latch the part into one of the four central processor unit (cpu) controlled modes of operation. the lir output can be used as an aid to debugging once reset is completed. the open-drain lir pin goes to an active low during the first e-clock cycle of each instruction and remains low for the duration of that cycle. the v stby input is used to retain random-access memory (ram) contents during power down. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description read/write (r/w) mc68hc711d3 ? rev. 2 data sheet motorola general description 19 1.12 read/write (r/w ) this pin performs either of two separate functions, depending on the operating mode. in single-chip and bootstrap modes, r/w functions as input/output port d bit 7. refer to section 5. input/output (i/o) ports for further information. in expanded multiplexed and test modes, r/w performs a read/write function. r/w controls the direction of transfers on the external data bus. 1.13 port d bit 6/ad dress strobe (pd6/as) this pin performs either of two separate functions, depending on the operating mode. in single-chip and bootstrap modes, the pin functions as input/output port d bit 6. in the expanded multiplexed and test modes, it provides an address strobe (as) function. as is used to demul tiplex the address and data signals at port c. refer to section 2. operating modes and memory for further information. 1.14 input/output lines (pa7?p a0, pb7?pb0, pc7?pc0, and pd7?pd0) in the 44-pin plcc package, 32 input/output lines are arranged into four 8-bit ports: a, b, c, and d. the lines of ports b, c, and d are fully bidirectional. port a has two bidirectional, three input-only, and three output-only lines in the 44-pin plcc packaging. in the 40-pin dip, two of the output-only lines are not bonded. each of these four ports serves a purpose other than input/output (i/o), depending on the operating mode or peripheral functions selected. note: ports b, c, and two bits of port d are avai lable for i/o functions only in single-chip and bootstrap modes. refer to table 1-1 for details about the functions of the 32 port signals within different operating modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc711d3 ? rev. 2 20 general description motorola table 1-1. port signal functions port/bit single-chip and bootstrap mode expanded multiplexed and special test mode pa 0 pa 0 / i c 3 pa 1 pa 1 / i c 2 pa 2 pa 2 / i c 1 pa3 pa3/oc5/ic4/and-or oc1 pa 4 (1) 1. in the 40-pin package, pins pa4 and pa6 ar e not bonded. their associated i/o and output compare functions are not available externally. they can still be used as internal software timers, however. pa4/oc4/and-or oc1 pa5 pa5/oc3/and-or oc1 pa 6 (1) pa6/oc2/and-or oc1 pa7 pa7/pai/and-or oc1 pb0 pb0 a8 pb1 pb1 a9 pb2 pb2 a10 pb3 pb3 a11 pb4 pb4 a12 pb5 pb5 a13 pb6 pb6 a14 pb7 pb7 a15 pc0 pc0 a0/d0 pc1 pc1 a1/d1 pc2 pc2 a2/d2 pc3 pc3 a3/d3 pc4 pc4 a4/d4 pc5 pc5 a5/d5 pc6 pc6 a6/d6 pc7 pc7 a7/d7 pd0 pd0/rxd pd1 pd1/txd pd2 pd2/miso pd3 pd3/mosi pd4 pd4/sck pd5 pd5/ss pd6 pd6 as pd7 pd7 r/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 21 data sheet ? mc68hc711d3 section 2. operatin g modes and memory 2.1 introduction this section contains information about: the modes that define mc68hc711d3 operating conditions the on-chip memory that allows the microcontroller unit (mcu) to be configured for various applications the 4-kbytes of programmable read-only memory (prom) 2.2 operating modes the mc68hc711d3 uses two dedicated pins, moda and modb, to select one of two normal operating modes or one of two special operating modes. a value reflecting the microcontroller unit (mcu) status or mode selected is latched on bits smod and mda of the highest priority i-bit interrupt and miscellaneous register (hprio) on the rising edge of reset. the normal operating modes are the single-chip and expanded-multiplexed modes. the special operating modes are the bootstrap and test modes. table 2-1 shows mode selection according to the values encoded on the moda and modb pins, and the value latched in the smod and mda bits. 2.2.1 single-chip mode in single-chip mode, the mcu functions as a self-contained microcontroller and has no external address or data bus. the 4-kbyte erasable programmable read-only memory (eprom) would contain all program code and is located at $f000?$ffff. this mode provides maximum use of the pins for on-chip peripheral functions, and all the address and data activity occurs within the mcu. table 2-1. mode selection reset moda modb mode selected smod mda 1 0 1 normal ? single chip 0 0 1 1 1 normal ? expanded multiplexed 0 1 1 0 0 special ? bootstrap (boot) 1 0 1 1 0 special ? test 1 1 0 0 0 reserved x x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 22 operating modes and memory motorola 2.2.2 expanded multiplexed mode in the expanded-multiplexed mode, the mcu can address up to 64 kbytes of address space. high-order address bits are output on the port b pins. low-order address bits and the bidirectional data bus are multiplexed on port c. the as pin provides the control output used in demultiplexing the low-order address. the r/w pin is used to control the direction of data transfer on the port c bus. if this mode is entered out of reset, the eprom is located at $7000?$7fff and vector accesses are from external me mory. to be in expanded-multiplexed mode with eprom located at $f000?$ffff, it is necessary to start in single-chip mode, executing out of eprom, and then set the mda bit of the hprio register to switch mode. note: r/w , as, and the high-order address bus (port b) are inputs in single-chip mode. these inputs may need to be pulled up so that off-chip accesses cannot occur while the mcu is in single-chip mode. 2.2.3 special bootstrap mode (boot) this special mode is similar to single- chip mode. the resident bootloader program contains a 256-byte program in a specia l on-chip read-only memory (rom). the user downloads a small program into on -board ram using the sci port. program control is passed to ram when an idle line of at least four characters occurs. in this mode, all interrupt vectors are mapped to ram (see table 2-2 ), so that the user can set up a jump table, if desired. bootstrap mode (boot) is entered out of reset if the voltage level on both moda and modb is low. the programming aspec t of bootstrap mode, used to program the one-time programmable rom (otpro m) through the mcu, is entered automatically if irq is low and programming voltage is available on the v pp pin. irq should be pulled up while in reset with moda and modb configured for bootstrap mode to prevent unint entional programming of the eprom. this versatile mode (boot) can be used for test and diagnostic functions on completed modules and for programming the on-board prom. the serial receive logic is initialized by software in th e bootloader rom, which provides program control for the sci baud rate and word format. mode switching to other modes can occur under program control by writing to the smod and mda bits of the hprio register. two special bootloader functions allow either an immediate jump-to-ram at memory address $0000 or an immediate jump-to-eprom at $f000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory operating modes mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 23 2.2.4 special test mode this special expanded mode is primarily in tended or production testing. the user can access a number of special test contro l bits in this mode. reset and interrupt vectors are fetched externally from lo cations $bfc0?$bfff. a switch can be made from this mode to other modes under program control. table 2-2. bootstrap mode jump vectors address vector 00c4 sci 00c7 spi 00ca pulse accumulator input edge 00cd pulse accumulator overflow 00d0 timer overflow 00d3 timer output compare 5/input capture 4 00d6 timer output compare 4 00d9 timer output compare 3 00dc timer output compare 2 00df timer output compare 1 00e3 timer input capture 3 00e5 timer input capture 2 00e8 timer input capture 1 00eb real-time interrupt 00ee irq 00f1 xirq 00f4 swi 00f7 illegal opcode 00fa cop fail 00fd clock monitor bf00 (boot) reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 24 operating modes and memory motorola 2.3 memory map figure 2-1 illustrates the memory map for both normal modes of operation (single-chip and expanded-multiplexed), as well as for both special modes of operation (bootstrap and test). in the single-chip mode, the mcu does not generate external addresses. the internal memory locations are shown in the shaded areas, and the contents of these shaded areas are explained on the right side of the diagram. in expanded-multiplexed mode, the memory locations are basically the same as in the single-chip mode except that the memory locations between shaded areas are for externally addressed memory and i/o. the special bootstrap mode is similar to the single-chip mode, except that the bootstrap program rom is located at memory locations $bf00?$bfff, vectors included. the special test mode is similar to the expanded-multiplexed mode except the interrupt vectors are at external memory locations. figure 2-1. mc68hc711d3 memory map single chip special special test expanded 192 bytes static ram internal registers and i/o special modes interrupt vectors 4 kbytes prom (rom) 256-bytes boot rom $bfc0 $bfff $bf00 $bfff $7000 $7fff $0040 $00ff $0000 $003f $0000 $1000 $2000 $3000 $4000 $5000 $6000 $7000 $8000 $9000 $a000 $b000 $c000 $d000 $e000 $f000 $ffff multiplexed bootstrap external external (may be mapped to any 4-k boundary using init register) (may be mapped to any 4-k boundary using the init register) present at reset and may be disabled by epon (rom on) bit in config register. interrupt vectors are external. normal modes interrupt vectors 4-kbytes prom (rom) $bfc0 $bfff $bf00 $bfff modb moda mode selected 1 1 0 0 0 1 0 1 single-chip (mode 0) expanded multiplexed (mode 1) special bootstrap special test f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory memory map mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 25 2.3.1 control and status registers figure 2-2 is a representation of all 64 bytes of control and status registers, i/o and data registers, and reserved locations that make up the internal register block. this block may be mapped to any 4-k boundary in memory, but reset locates it at $0000?$003f. this mappability factor and the default starting addresses are indicated by the use of a bold 0 as the starting character of a register?s address. addr. register name bit 7654321bit 0 $ 0 000 port a data register (porta) see page 68. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: hi-z 0 0 0 hi-z hi-z hi-z hi-z $ 0 001 reserved rrrrrrrr $ 0 002 port c control register (pioc) see page 70. read: 00cwom00000 write: reset:00000000 $ 0 003 port c data register (portc) see page 70. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: reset configures pins as hi-z inputs $ 0 004 port b data register (portb) see page 69. read: pb7 pb6 pb5 pb4 pb3 bp2 bp1 pb0 write: reset: reset configures pins as hi-z inputs $ 0 005 reserved rrrrrrrr $ 0 006 data direction register for port b (ddrb) see page 69. read: ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 write: reset:00000000 $ 0 007 data direction register for port c (ddrc) see page 71. read: ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 write: reset:00000000 $ 0 008 port d data register (portd) see page 71. read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 $ 0 009 data direction register for port d (ddrd) see page 72. read: ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 write: reset:00000000 $ 0 00a reserved rrrrrrrr = unimplemented r = reserved u = unaffected figure 2-2. register and control bit assignments (sheet 1 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 26 operating modes and memory motorola $ 0 00b timer compare force register (cforc) see page 104. read: foc1 foc2 foc3 foc4 foc5 0 0 0 write: reset:00000000 $ 0 00c output compare 1 mask register (oc1m) see page 105. read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 write: reset:00000000 $ 0 00d output compare 1 data register (oc1d) see page 105. read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 write: reset:00000000 $ 0 00e timer counter register high (tcnt) see page 106. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $ 0 00f timer counter register low (tcnt) see page 106. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $ 0 010 timer input capture register 1 high (tic1) see page 100. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $ 0 011 timer input capture register 1 low (tic1) see page 100. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $ 0 012 timer input capture register 2 high (tic2) see page 100. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $ 0 013 timer input capture register 2 low (tic2) see page 100. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $ 0 014 timer input capture register 3 high (tic3) see page 100. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $ 0 015 timer input capture register 3 low (tic3) see page 100. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $ 0 016 timer output compare register 1 high (toc1) see page 103. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 15 write: reset:11111111 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. register and control bit assignments (sheet 2 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory memory map mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 27 $ 0 017 timer output compare register 1 low (toc1) see page 103. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $ 0 018 timer output compare register 2 high (toc2) see page 103. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $ 0 019 timer output compare register 2 low (toc2) see page 103. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 $ 0 01a timer output compare register 3 high (toc3) see page 103. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $ 0 01b timer output compare register 3 low (toc3) see page 103. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $ 0 01c timer output compare register 4 high (toc4) see page 103. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $ 0 01d timer output compare register 4 low (toc4) see page 103. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $ 0 01e timer input capture 4/ output compare 5 register high (ti4/o5) see page 101. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $ 0 01f timer input capture 4/ output compare 5 register low (ti4/o5) see page 101. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 $ 0 020 timer control 1 register (tctl1) see page 106. read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset:00000000 $ 0 021 timer control register 2 (tctl2) see page 99. read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. register and control bit assignments (sheet 3 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 28 operating modes and memory motorola $ 0 022 timer interrupt mask 1 register (tmsk1) see page 107. read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset:00000000 $ 0 023 timer interrupt flag 1 register (tflg1) see page 108. read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset:00000000 $ 0 024 timer interrupt mask 2 register (tmsk2) see page 108. read: toi rtii paovi paii 0 0 pr1 pr0 write: reset:00000000 $ 0 025 timer interrupt flag 2 register (tflg2) see page 109. read: tof rtif paovf paif 0 0 0 0 write: reset:00000000 $ 0 026 pulse accumulator control r e g i s t er (pa c t l ) see p ag e s 1 12 a nd 1 14. read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 $ 0 027 pulse accumulator count register (pacnt) see page 115. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset $ 0 028 spi control register (spcr) see page 92. read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu $ 0 029 spi status register (spsr) see page 93. read: spifwcol0modf0000 write: reset:00000000 $ 0 02a spi data i/o register (spdr) see page 94. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset $ 0 02b baud rate register (baud) see page 81. read: tclr 0 scp1 scp0 rckb scr2 scr1 scr0 write: reset:00000uuu $ 0 02c sci control register 1 (sccr1) see page 78. read: r8 t8 0 m wake 0 0 0 write: reset:uu000000 $ 0 02d sci control register 2 (sccr2) see page 79. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. register and control bit assignments (sheet 4 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory memory map mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 29 $ 0 02e sci status register (scsr) see page 80. read: tdre tc rdrf idle or nf fe 0 write: reset:11000000 $ 0 02f sci data register (scdr) see page 78. read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: unaffected by reset $ 0 030 $ 0 038 reserved rrrrrrrr $ 0 039 system configuration options register (option) see page 53. read: 0 0 irqe dly cme 0 cr1 cr0 write: reset:00010000 $ 0 03a arm/reset cop timer circuitry register (coprst) see page 52. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $ 0 03b prom programming control register (pprog) see page 33. read: mbe 0 elat excol exrow 0 0 pgm write: reset:00000000 $ 0 03c highest priority i-bit interrupt and miscellaneous register (hprio) see page 63. read: rboot smod mda irvne psel3 psel2 psel1 psel0 write: reset: note 1 0 1 0 1 1. the values of the rboot, smod, irvne, and mda bits at reset depend on the mode during initialization. refer to table 4-3. hardware mode select summary . $ 0 03d ram and i/o mapping register (init) see page 30. read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset:00000001 $ 0 03e test 1 register (test) read: tilop 0 occ4 cbyp disr fcm fcop 0 write: reset:00000000 $ 0 03f system configuration register (config) see page 31. read: 00000nocopromon0 write: reset:00000uu0 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. register and control bit assignments (sheet 5 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 30 operating modes and memory motorola 2.3.2 ram and i/o mapping register the random-access memory (ram) and input/output (i/o) mapping register (init) is a special-purpose 8-bit r egister that is used during initialization to change the default locations of ram and control registers within the mcu memory map. it can be written to only once within the first 64 e-clock cycles after a reset in normal modes. thereafter, it becomes a read-only register. ram2?ram0 (init bits 7?4) specify the star ting address for the 192 bytes of static ram. reg3?reg0 (init bits 3?0) specify the starting address for the control and status register block. in each case, the four ram or reg bits become the four upper bits of the 16-bit address of the ram or register. since the init register is set to $00 by reset, the internal registers begin at $0000 and ram begins at $0040. throughout this document, control and status register addresses are displayed with the high-order digit shown as a bold 0 . this convention indicates that the register block may be relocated to any 4-k memory page, but that its default location is $0000. ram and the control and status registers can be relocated independently. if the control and status registers are relocated in such a way as to conflict with prom, then the register block takes priority , and the eprom or otprom at those locations becomes inaccessible. no harmf ul conflicts result. lower priority resources simply become inaccessible. simila rly, if an internal resource conflicts with an external device, no harmful conflict results, since data from the external device is not applied to the internal dat a bus. thus, it cannot interfere with the internal read. note: there are unused register locations in the 64- byte control and status register block. reads of these unused registers return data from the undriven internal data bus, not from another source that happens to be located at the same address. 2.3.3 configuration control register the configuration control register (confi g) controls the presence of otprom or eprom in the memory map and enables the computer operating properly (cop) watchdog system. this register is writable only once in expanded and single-chip modes (smod = 0). in these mode, the cop watchdog timer is enabled out of reset. in all modes, except normal expanded, eprom is enabled and located at $f000?$ffff. in address: $ 0 03d bit 7654321bit 0 read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset:00000000 figure 2-3. ram and i/o mapping register (init) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory programmable read-only memory (prom) mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 31 normal expanded mode, eprom is enabled and located at $7000?$7fff. should the user wish to be in expanded mode, but with eprom mapped at $f000?$ffff, he must reset in single-chip mode, and write a 1 to the mda bit in the hprio register. bits 7?3 and 0 ? not implemented always read 0. nocop ? computer operating properly system disable bit this bit is cleared out of reset in normal modes (single chip and expanded), enabling the cop system. it is writable only once after reset in these modes (smod = 0). in the special modes (test and bootstrap) (smod = 1), this bit comes out of reset set, and is writable any time. 1 = cop system is disabled. 0 = cop system is enabled, reset forced on timeout. romon ? prom enable bit this bit is set out of reset, enabling t he eprom or otprom in all modes. this bit is writable once in norma l modes (smod = 0), but is writable at any time in special modes (smod = 1). 1 = prom is present in the memory map. 0 = prom is disabled from the memory map. note: in expanded mode out of reset, the eprom or otprom is located at $7000?$7fff. in all other modes, the prom resides at $f000?$ffff. 2.4 programmable read- only memory (prom) the mc68hc711d3 has 4-kbytes of one-time programmable read-only memory (otprom). the prom address is $f 000?$ffff in all modes except expanded multiplexed. in expanded- multiplexed mode, the prom is located at $7000?$7fff after reset. the on-chip read-only memory (rom) of an mc68hc711d3 is programmed in mcu mode. in this mode, the prom is programmed through the mcu in the bootstrap or test modes. the erased state of a prom byte is $ff. using the on-chip otprom programming feature requires an external 12-volt nominal power supply (v pp ). normal programming is accomplished using the otprom programming register (pprog). address: $ 0 03f bit 7654321bit 0 read: 00000nocopromon0 write: reset:00000uu0 u = unaffected figure 2-4. configuration control register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 32 operating modes and memory motorola as described in the following subsections , these two methods of programming and verifying eprom are possible: 1. programming an individual eprom address 2. programming the eprom with downloaded data 2.4.1 programming an individual eprom address in this method, the mcu programs it s own eprom by controlling the pprog register. use these procedures to program the eprom through the mcu with: the romon bit set in the config register the 12-volt nominal programming voltage present on the xirq /v pp pin the irq pin must be pulled high. eprog ldab #$20 stab $003b set elat bit (pgm = 0) to enable eprom latches. staa $0,x store data to eprom address ldab #$21 stab $003b set pgm bit with elat = 1 to enable eprom programming voltage jsr dlyep delay 2?4 ms clr $003b turn off programming voltage and set to read mode 2.4.2 programming the eprom with downloaded data when using this method, the eprom is programmed by software while in the special test or bootstrap modes. user-developed software can be uploaded through the sci or a rom-resident eprom programming utility can be used. the 12-volt nominal programming volta ge must be present on the xirq /v pp pin. to use the resident utility, bootload a 3-byte program consisting of a single jump instruction to $bf00. $bf00 is the starting address of a resident eprom programming utility. the utility program se ts the x and y index registers to default values, then receives programming data from an external host, and puts it in eprom. the value in ix determines programm ing delay time. the value in iy is a pointer to the first address in eprom to be programmed (default = $f000). when the utility program is ready to rece ive programming data, it sends the host the $ff character. then it waits. when the host sees the $ff character, the eprom programming data is sent, starting with the first location in the eprom array. after the last byte to be programmed is sent and the corresponding verification data is returned, the programmi ng operation is terminated by resetting the mcu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory programmable read-only memory (prom) mc68hc711d3 ? rev. 2 data sheet motorola operating modes and memory 33 2.4.3 prom programming control register the prom programming control register (pprog) is used to control the programming of the otprom or eprom. pprog is cleared on reset so that the prom is configured for normal read. mbe ? multiple byte program enable bit this bit is reserved for testing. bit 6, 2, and 1 ? not implemented always read 0. elat ? eprom (otprom) latch control bit 1 = prom address and data bus are configured for programming. writes to prom cause address and data to be latched. the prom cannot be read. 0 = prom address and data bus are configured for normal reads. prom cannot be programmed. excol ? select extra columns bit this bit is reserved for testing. exrow ? select extra row bit this bit is reserved for testing. pgm ? eprom (otprom) program command bit this bit may be written only when elat = 1. 1 = programming power is switched on to prom array. 0 = programming power is switched off. address: $ 0 03b bit 7654321bit 0 read: mbe 0 elat excol exrow 0 0 pgm write: reset:00000000 figure 2-5. prom programming control register (pprog) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and memory data sheet mc68hc711d3 ? rev. 2 34 operating modes and memory motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 35 data sheet ? mc68hc711d3 section 3. central processor unit (cpu) 3.1 introduction this section presents information on m68hc11 central processor unit (cpu): architecture data types addressing modes instruction set special operations such as subroutine calls and interrupts the cpu is designed to treat all peripheral, input/output (i/o), and memory locations identically as addresses in the 64-kbyte memory map. this is referred to as memory-mapped i/o. i/o has no instru ctions separate from those used by memory. this architecture also allows accessing an operand from an external memory location with no execution time penalty. 3.2 cpu registers m68hc11 cpu registers are an integral part of the cpu and are not addressed as if they were memory locations. the seven registers, discussed in the following paragraphs, are shown in figure 3-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 36 central processor unit (cpu) motorola figure 3-1. programming model 3.2.1 accumulators a, b, and d accumulators a and b are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. for some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator d. although most instructions can use accumulators a or b interchangeably, these exceptions apply: the abx and aby instructions add the contents of 8-bit accumulator b to the contents of 16-bit register x or y, but there are no equivalent instructions that use a instead of b. the tap and tpa instructions transfer data from accumulator a to the condition code register or from the cond ition code register to accumulator a. however, there are no equivalent instructions that use b rather than a. the decimal adjust accumulator a (daa) instruction is used after binary-coded decimal (bcd) arithmetic operations, but there is no equivalent bcd instruction to adjust accumulator b. the add, subtract, and compare instructions associated with both a and b (aba, sba, and cba) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. a:b 70 70 15 0 accumulator a accumulator b double accumulator d index register x index register y stack pointer program counter 70 c v z n i h x s d ix iy sp pc carry overflow zero negative i interrupt mask half carry (from bit 3) x interrupt mask stop disable ccr 15 15 15 15 0 0 0 0 condition code register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 37 3.2.2 index register x (ix) the ix register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. the ix register can also be used as a counter or as a temporary storage register. 3.2.3 index register y (iy) the 16-bit iy register performs an indexed mode function similar to that of the ix register. however, most instructions using the iy register require an extra byte of machine code and an extra cycl e of execution time because of the way the opcode map is implemented. refer to 3.4 opcodes and operands for further information. 3.2.4 stack pointer (sp) the m68hc11 cpu has an automatic program stack. this stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system. normally, the sp is in itialized by one of the first instructions in an application program. the stack is configured as a data structure that grows downward from high memory to low memory. each time a new byte is pushed onto the stack, the sp is decremented. each time a byte is pulled from the stack, the sp is incremented. at any given time, the sp holds the 16-bit address of the next free location in the stack. figure 3-2 is a summary of sp operations. when a subroutine is called by a jump-to-subroutine (jsr) or branch-to- subroutine (bsr) instruction, the address of the instruction after the jsr or bsr is automatically pushed onto the stack, l east significant byte first. when the subroutine is finished, a re turn-from-subroutine (rts) instruction is executed. the rts pulls the previously stacked return addr ess from the stack and loads it into the program counter. execution then continues at this recovered return address. when an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the cpu registers are pushed onto th e stack, and execution continues at the address specified by the vector for the interrupt. at the end of the interrupt service routine, a return-from interrupt (rti) instruction is executed. the rti instruction causes the saved registers to be pulled off the stack in reverse order. program execution resumes at the return address. certain instructions push and pull the a and b accumulators and the x and y index registers and are often used to preserve program context. for example, pushing accumulator a onto the stack when entering a subroutine that uses accumulator a and then pulling accumulator a off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 38 central processor unit (cpu) motorola figure 3-2. stacking operations sp-9 stack sp-1 acmltr a acmltr b condition code sp-2 sp-3 sp-4 sp-5 sp-6 sp-7 sp-8 index register (y l ) index register (y h ) index register (x l ) index register (x h ) rtn l rtn h stack sp-2 sp-1 sp rtn l rtn h stack sp-2 sp-1 sp rtn l rtn h $9d = jsr dd next main instr direct main program $ad = jsr ff next main instr indxd,x main program pc rtn pc rtn $18 = pre ff next main instr indxd,y main program pc rtn $ad = jsr $bd = jsr ll next main instr extend main program pc rtn hh $8d = bsr rr next main instr main program $39 = rts subroutine pc rtn pc bsr, branch to subroutine stack sp sp+1 sp+2 rts, return from subroutine $3f = swi main program pc swi, software interrupt rtn $3e = wai main program pc wai, wait for interrupt rtn $3b = rti interrupt program pc stack sp+1 sp rti, return from interrupt acmltr a acmltr b condition code sp+2 sp+3 sp+4 sp+5 sp+6 sp+7 sp+8 sp+9 legend: rtn rtn h rtn l dd ff hh ll rr address of next instruction in main program to be executed upon return from subroutine most significant byte of return address least significant byte of return address 8-bit direct address ($0000?$00ff) (high byte assumed to be $00). 8-bit positive offset $00 (0) to $ff (256) is added to index. high-order byte of 16-bit extended address. low-order byte of 16-bit extended address. signed-relative offset $80 (?128) to $7f (+127) (offset relative to the address following the machine code offset byte). jsr, jump to subroutine shaded cells show stack pointer position after operation is complete. rtn l rtn h index register (y l ) index register (y h ) index register (x l ) index register (x h ) rtn l rtn h sp $6e = jmp ff main program next instruction indxd,x pc x + ff $18 = pre ff main program pc $6e = jmp jmp, jump next instruction x + ff indxd,y $7e = jmp ll main program pc hh next instruction hh ll extnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 39 3.2.5 program counter (pc) the program counter, a 16-bit register, contai ns the address of the next instruction to be executed. after reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. see table 3-1 . 3.2.6 condition code register (ccr) this 8-bit register contains: five condition code indicators (c, v, z, n, and h) two interrupt masking bits (irq and xirq ) one stop disable bit (s) in the m68hc11 cpu, condition codes are updated automatically by most instructions. for example, load accumulator a (ldaa) and store accumulator a (staa) instructions automatically set or clear the n, z, and v condition code flags. pushes, pulls, add b to x (abx), ad d b to y (aby), and transfer/exchange instructions do not affect the condition codes. refer to table 3-2 , which shows what condition codes are affected by a particular instruction. 3.2.6.1 carry/borrow (c) the c bit is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation. the c bit also acts as an error flag for multiply and divide operations. shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.2.6.2 overflow (v) the overflow bit is set if an operation ca uses an arithmetic overflow. otherwise, the v bit is cleared. 3.2.6.3 zero (z) the z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. otherwise, the z bit is cleared. com pare instructions do an internal implied subtraction and the condition codes, incl uding z, reflect the results of that subtraction. a few operations (inx, dex, iny, and dey) affect the z bit and no other condition flags. for these operations, only = and conditions can be determined. table 3-1. reset vector comparison mode por or reset pin clock monitor cop watchdog normal $fffe, $ffff $fffc, $fffd $fffa, $fffb test or boot $bffe, $bfff $ bffc, $fffd $bffa, $fffb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 40 central processor unit (cpu) motorola 3.2.6.4 negative (n) the n bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (msb = 1). otherwise, the n bit is cleared. a result is said to be negative if its most significant bit (msb) is a 1. a quick way to test whether the contents of a memory location has the msb set is to load it into an accumulator and then check the status of the n bit. 3.2.6.5 i-interrupt mask (i) the interrupt request (irq) mask (i bit) is a global mask that disables all maskable interrupt sources. while the i bit is set, interrupts can become pending, but the operation of the cpu continues uninterrupted until the i bit is cleared. after any reset, the i bit is set by default and can be cleared only by a software instruction. when an interrupt is recognized, the i bit is set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, a return-from-interrupt instruct ion is normally executed, restoring the registers to the values that were present before the interrupt occurred. normally, the i bit is 0 after a return from interrupt is executed. al though the i bit can be cleared within an interrupt service routine, "nesting" interr upts in this way should be done only when there is a clear understanding of latency a nd of the arbitration mechanism. refer to section 4. resets, interrupts, and low-power modes . 3.2.6.6 half carry (h) the h bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an add, aba, or adc instruction. otherwise, the h bit is cleared. half carry is used during bcd operations. 3.2.6.7 x-interrupt mask (x) the xirq mask (x) bit disables interrupts from the xirq pin. after any reset, x is set by default and must be cleared by a software instruction. when an xirq interrupt is recognized, the x and i bits are set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, an rti instruction is normally executed, causing t he registers to be restored to the values that were present before the interrupt occurred. the x interrupt mask bit is set only by hardware (reset or xirq acknowledge). x is cleared only by program instruction (tap, where the associated bit of a is 0; or rti, where bit 6 of the value loaded into the ccr from the stack has been cleared). there is no hardware action for clearing x. 3.2.6.8 stop disable (s) setting the stop disable (s) bit prevents the stop instruction from putting the m68hc11 into a low-power stop condition. if the stop instruction is encountered by the cpu while the s bit is set, it is treated as a no-operation (nop) instruction, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data types mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 41 and processing continues to the next instruction. s is set by reset; stop is disabled by default. 3.3 data types the m68hc11 cpu supports four data types: 1. bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses a byte is eight bits wide and can be ac cessed at any byte location. a word is composed of two consecutive bytes with the most significant byte at the lower value address. because the m68hc11 is an 8-bit cpu, there are no special requirements for alignment of instructions or operands. 3.4 opcodes and operands the m68hc11 family of microcontrollers uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to provide each instruction with a range of addressing capabilities. only 256 opcodes w ould be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. a 4-page opcode map has been implemented to expand the number of instructions. an additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. as its name implies, the additional byte precedes the opcode. a complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. the operands contain in formation the cpu needs for executing the instruction. complete instructions can be from one to five bytes long. 3.5 addressing modes six addressing modes can be used to access memory: 1. immediate 2. direct 3. extended 4. indexed 5. inherent 6. relative these modes are detailed in the followin g paragraphs. all modes except inherent mode use an effective address. the effectiv e address is the memory address from f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 42 central processor unit (cpu) motorola which the argument is fetched or stored or the address from which execution is to proceed. the effective address can be specified within an instruction, or it can be calculated. 3.5.1 immediate in the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. the num ber of bytes following the opcode matches the size of the register or memory location being operated on. there are 2-, 3-, and 4- (if prebyte is required) by te immediate instructions. the effective address is the address of the byte following the instruction. 3.5.2 direct in the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. addresses $00?$ff are thus accessed directly, using 2-byte instructions. execution time is reduced by eliminating the additional memory access required for the high-order address byte. in most applications, this 256-byte area is reserved for frequently referenced data. in m68hc11 mcus, the memory map can be configured for combinations of internal registers, ram, or external memory to occupy these addresses. 3.5.3 extended in the extended addressing mode, the effective address of the argument is contained in two bytes follow ing the opcode byte. these are 3-byte instructions (or 4-byte instructions if a prebyte is required). one or two bytes are needed for the opcode and two for the effective address. 3.5.4 indexed in the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (ix or iy). the sum is the effective address. this addressi ng mode allows referencing any memory location in the 64-kbyte address space. these are 2- to 5-byte instructions, depending on whether a prebyte is required. 3.5.5 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations that use only the index registers or accumulators, as well as control instru ctions with no arguments, are included in this addressing mode. these are 1- or 2-byte instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 43 3.5.6 relative the relative addressing mode is used only for branch instructions. if the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. otherwise, control proceeds to the next instruction. these are usually 2-byte instructions. 3.6 instruction set refer to table 3-2 , which shows all the m68hc11 instructions in all possible addressing modes. for each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in cpu e-clock cycles. table 3-2. instruction set (sheet 1 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c aba add accumulators a + b ? ainh1b?2?? ? ? ???? abx add b to x ix + (00 : b) ? ix inh 3a ? 3 ???????? aby add b to y iy + (00 : b) ? iy inh 18 3a ? 4 ???????? adca (opr) add with carry to a a + m + c ? aa imm adir aext aind,x aind,y 89 99 b9 a9 18 a9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adcb (opr) add with carry to b b + m + c ? bb imm bdir bext bind,x bind,y c9 d9 f9 e9 18 e9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adda (opr) add memory to a a + m ? a a imm adir aext aind,x aind,y 8b 9b bb ab 18 ab ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addb (opr) add memory to b b + m ? bbimm bdir bext bind,x bind,y cb db fb eb 18 eb ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addd (opr) add 16-bit to d d + (m : m + 1) ? dimm dir ext ind,x ind,y c3 d3 f3 e3 18 e3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? anda (opr) and a with memory a m ? aa imm a dir a ext aind,x aind,y 84 94 b4 a4 18 a4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? andb (opr) and b with memory b m ? bbimm bdir bext bind,x bind,y c4 d4 f4 e4 18 e4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? asl (opr) arithmetic shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? c 0 b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 44 central processor unit (cpu) motorola asla arithmetic shift left a a inh 48 ? 2 ???? ???? aslb arithmetic shift left b b inh 58 ? 2 ???? ???? asld arithmetic shift left d inh 05 ? 3 ? ? ? ? ???? asr arithmetic shift right ext ind,x ind,y 77 67 18 67 hh ll ff ff 6 6 7 ???? ???? asra arithmetic shift right a a inh 47 ? 2 ???? ???? asrb arithmetic shift right b b inh 57 ? 2 ???? ???? bcc (rel) branch if carry clear ? c = 0 rel 24 rr 3 ???????? bclr (opr) (msk) clear bit(s) m (mm ) ? m dir ind,x ind,y 15 1d 18 1d dd mm ff mm ff mm 6 7 8 ???? ?? 0? bcs (rel) branch if carry set ? c = 1 rel 25 rr 3 ???????? beq (rel) branch if = zero ? z = 1 rel 27 rr 3 ? ? ? ? ? ? ? ? bge (rel) branch if ? zero ? n v = 0 rel 2c rr 3 ???????? bgt (rel) branch if > zero ? z + (n v) = 0 rel 2e rr 3 ???????? bhi (rel) branch if higher ? c + z = 0 rel 22 rr 3 ???????? bhs (rel) branch if higher or same ? c = 0 rel 24 rr 3 ???????? bita (opr) bit(s) test a with memory a m a imm adir aext aind,x aind,y 85 95 b5 a5 18 a5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? bitb (opr) bit(s) test b with memory b m b imm bdir bext bind,x bind,y c5 d5 f5 e5 18 e5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ble (rel) branch if ? zero ? z + (n v) = 1 rel 2f rr 3 ???????? blo (rel) branch if lower ? c = 1 rel 25 rr 3 ???????? bls (rel) branch if lower or same ? c + z = 1 rel 23 rr 3 ???????? blt (rel) branch if < zero ? n v = 1 rel 2d rr 3 ???????? bmi (rel) branch if minus ? n = 1 rel 2b rr 3 ???????? bne (rel) branch if not = zero ? z = 0 rel 26 rr 3 ???????? bpl (rel) branch if plus ? n = 0 rel 2a rr 3 ???????? bra (rel) branch always ? 1 = 1 rel 20 rr 3 ???????? brclr(opr) (msk) (rel) branch if bit(s) clear ? m mm = 0 dir ind,x ind,y 13 1f 18 1f dd mm rr ff mm rr ff mm rr 6 7 8 ???????? brn (rel) branch never ? 1 = 0 rel 21 rr 3 ???????? table 3-2. instruction set (sheet 2 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 45 brset(opr) (msk) (rel) branch if bit(s) set ? (m ) mm = 0 dir ind,x ind,y 12 1e 18 1e dd mm rr ff mm rr ff mm rr 6 7 8 ???????? bset (opr) (msk) set bit(s) m + mm ? mdir ind,x ind,y 14 1c 18 1c dd mm ff mm ff mm 6 7 8 ???? ?? 0? bsr (rel) branch to subroutine see figure 3-2 rel 8d rr 6 ???????? bvc (rel) branch if overflow clear ? v = 0 rel 28 rr 3 ???????? bvs (rel) branch if overflow set ? v = 1 rel 29 rr 3 ???????? cba compare a to b a ? b inh 11 ? 2 ? ? ? ? ???? clc clear carry bit 0 ? c inh 0c ? 2 ??????? 0 cli clear interrupt mask 0 ? i inh 0e ? 2 ??? 0 ???? clr (opr) clear memory byte 0 ? mext ind,x ind,y 7f 6f 18 6f hh ll ff ff 6 6 7 ???? 0 1 0 0 clra clear accumulator a 0 ? a a inh 4f ? 2 ? ? ? ? 0 1 0 0 clrb clear accumulator b 0 ? b b inh 5f ? 2 ? ? ? ? 0 1 0 0 clv clear overflow flag 0 ? v inh 0a ? 2 ?????? 0 ? cmpa (opr) compare a to memory a ? m a imm adir aext aind,x aind,y 81 91 b1 a1 18 a1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? cmpb (opr) compare b to memory b ? m b imm bdir bext bind,x bind,y c1 d1 f1 e1 18 e1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? com (opr) ones complement memory byte $ff ? m ? mext ind,x ind,y 73 63 18 63 hh ll ff ff 6 6 7 ???? ?? 01 coma ones complement a $ff ? a ? aa inh 43 ? 2 ???? ?? 01 comb ones complement b $ff ? b ? bb inh 53 ? 2 ???? ?? 01 cpd (opr) compare d to memory 16-bit d ? m : m + 1 imm dir ext ind,x ind,y 1a 83 1a 93 1a b3 1a a3 cd a3 jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? cpx (opr) compare x to memory 16-bit ix ? m : m + 1 imm dir ext ind,x ind,y 8c 9c bc ac cd ac jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? cpy (opr) compare y to memory 16-bit iy ? m : m + 1 imm dir ext ind,x ind,y 18 8c 18 9c 18 bc 1a ac 18 ac jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? table 3-2. instruction set (sheet 3 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 46 central processor unit (cpu) motorola daa decimal adjust a adjust sum to bcd inh 19 ? 2 ? ? ? ? ???? dec (opr) decrement memory byte m ? 1 ? mext ind,x ind,y 7a 6a 18 6a hh ll ff ff 6 6 7 ???? ??? ? deca decrement accumulator a a ? 1 ? aainh 4a ? 2???? ??? ? decb decrement accumulator b b ? 1 ? bbinh 5a ? 2???? ??? ? des decrement stack pointer sp ? 1 ? sp inh 34 ? 3 ???????? dex decrement index register x ix ? 1 ? ix inh 09 ? 3 ? ? ? ? ? ? ?? dey decrement index register y iy ? 1 ? iy inh 18 09 ? 4 ? ? ? ? ? ? ?? eora (opr) exclusive or a with memory a m ? a a imm adir aext aind,x aind,y 88 98 b8 a8 18 a8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? eorb (opr) exclusive or b with memory b m ? b b imm bdir bext bind,x bind,y c8 d8 f8 e8 18 e8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? fdiv fractional divide 16 by 16 d / ix ? ix; r ? d inh 03 ? 41 ????? ??? idiv integer divide 16 by 16 d / ix ? ix; r ? d inh 02 ? 41 ????? ? 0 ? inc (opr) increment memory byte m + 1 ? mext ind,x ind,y 7c 6c 18 6c hh ll ff ff 6 6 7 ???? ??? ? inca increment accumulator a a + 1 ? a a inh 4c ? 2 ? ? ? ? ??? ? incb increment accumulator b b + 1 ? b b inh 5c ? 2 ? ? ? ? ??? ? ins increment stack pointer sp + 1 ? sp inh 31 ? 3 ???????? inx increment index register x ix + 1 ? ix inh 08 ? 3 ????? ? ?? iny increment index register y iy + 1 ? iy inh 18 08 ? 4 ????? ? ?? jmp (opr) jump see figure 3-2 ext ind,x ind,y 7e 6e 18 6e hh ll ff ff 3 3 4 ???????? jsr (opr) jump to subroutine see figure 3-2 dir ext ind,x ind,y 9d bd ad 18 ad dd hh ll ff ff 5 6 6 7 ???????? ldaa (opr) load accumulator a m ? a a imm a dir a ext a ind,x a ind,y 86 96 b6 a6 18 a6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? table 3-2. instruction set (sheet 4 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 47 ldab (opr) load accumulator b m ? b b imm b dir b ext b ind,x b ind,y c6 d6 f6 e6 18 e6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? ldd (opr) load double accumulator d m ? a,m + 1 ? bimm dir ext ind,x ind,y cc dc fc ec 18 ec jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? lds (opr) load stack pointer m : m + 1 ? sp imm dir ext ind,x ind,y 8e 9e be ae 18 ae jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldx (opr) load index register x m : m + 1 ? ix imm dir ext ind,x ind,y ce de fe ee cd ee jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0? ldy (opr) load index register y m : m + 1 ? iy imm dir ext ind,x ind,y 18 ce 18 de 18 fe 1a ee 18 ee jj kk dd hh ll ff ff 4 5 6 6 6 ???? ?? 0? lsl (opr) logical shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? lsla logical shift left a a inh 48 ? 2 ???? ???? lslb logical shift left b b inh 58 ? 2 ???? ???? lsld logical shift left double inh 05 ? 3 ? ? ? ? ???? lsr (opr) logical shift right ext ind,x ind,y 74 64 18 64 hh ll ff ff 6 6 7 ???? 0 ??? lsra logical shift right a a inh 44 ? 2 ???? 0 ??? lsrb logical shift right b b inh 54 ? 2 ???? 0 ??? lsrd logical shift right double inh 04 ? 3 ? ? ? ? 0 ??? mul multiply 8 by 8 a ? b ? d inh 3d ? 10 ??????? ? neg (opr) two?s complement memory byte 0 ? m ? mext ind,x ind,y 70 60 18 60 hh ll ff ff 6 6 7 ???? ???? nega two?s complement a 0 ? a ? aainh 40 ? 2???? ???? negb two?s complement b 0 ? b ? bbinh 50 ? 2???? ???? nop no operation no operation inh 01 ? 2 ? ? ? ? ? ? ? ? table 3-2. instruction set (sheet 5 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 48 central processor unit (cpu) motorola oraa (opr) or accumulator a (inclusive) a + m ? a a imm adir aext aind,x aind,y 8a 9a ba aa 18 aa ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? orab (opr) or accumulator b (inclusive) b + m ? b b imm bdir bext bind,x bind,y ca da fa ea 18 ea ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0? psha push a onto stack a ? stk,sp = sp ? 1 a inh 36 ? 3 ? ? ? ? ? ? ? ? pshb push b onto stack b ? stk,sp = sp ? 1 b inh 37 ? 3 ? ? ? ? ? ? ? ? pshx push x onto stack (lo first) ix ? stk,sp = sp ? 2 inh 3c ? 4 ???????? pshy push y onto stack (lo first) iy ? stk,sp = sp ? 2 inh 18 3c ? 5 ???????? pula pull a from stack sp = sp + 1, a ? stka inh 32 ? 4 ???????? pulb pull b from stack sp = sp + 1, b ? stkb inh 33 ? 4 ???????? pulx pull x from stack (hi first) sp = sp + 2, ix ? stk inh 38 ? 5 ???????? puly pull y from stack (hi first) sp = sp + 2, iy ? stk inh 18 38 ? 6 ???????? rol (opr) rotate left ext ind,x ind,y 79 69 18 69 hh ll ff ff 6 6 7 ???? ???? rola rotate left a a inh 49 ? 2 ? ? ? ? ???? rolb rotate left b b inh 59 ? 2 ? ? ? ? ???? ror (opr) rotate right ext ind,x ind,y 76 66 18 66 hh ll ff ff 6 6 7 ???? ???? rora rotate right a a inh 46 ? 2 ? ? ? ? ???? rorb rotate right b b inh 56 ? 2 ? ? ? ? ???? rti return from interrupt see figure 3-2 inh 3b ? 12 ??????? rts return from subroutine see figure 3-2 inh 39 ? 5 ???????? sba subtract b from a a ? b ? a inh 10 ? 2 ???? ???? sbca (opr) subtract with carry from a a ? m ? c ? aa imm adir aext aind,x aind,y 82 92 b2 a2 18 a2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? table 3-2. instruction set (sheet 6 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc711d3 ? rev. 2 data sheet motorola central processor unit (cpu) 49 sbcb (opr) subtract with carry from b b ? m ? c ? bb imm bdir bext bind,x bind,y c2 d2 f2 e2 18 e2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sec set carry 1 ? c inh 0d ? 2 ??????? 1 sei set interrupt mask 1 ? i inh 0f ? 2 ??? 1 ???? sev set overflow flag 1 ? v inh 0b ? 2 ?????? 1 ? staa (opr) store accumulator a a ? madir aext aind,x aind,y 97 b7 a7 18 a7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? stab (opr) store accumulator b b ? mbdir bext bind,x bind,y d7 f7 e7 18 e7 dd hh ll ff ff 3 4 4 5 ???? ?? 0? std (opr) store accumulator d a ? m, b ? m + 1 dir ext ind,x ind,y dd fd ed 18 ed dd hh ll ff ff 4 5 5 6 ???? ?? 0? stop stop internal clocks ? inh cf ? 2 ???????? sts (opr) store stack pointer sp ? m : m + 1 dir ext ind,x ind,y 9f bf af 18 af dd hh ll ff ff 4 5 5 6 ???? ?? 0? stx (opr) store index register x ix ? m : m + 1 dir ext ind,x ind,y df ff ef cd ef dd hh ll ff ff 4 5 5 6 ???? ?? 0? sty (opr) store index register y iy ? m : m + 1 dir ext ind,x ind,y 18 df 18 ff 1a ef 18 ef dd hh ll ff ff 5 6 6 6 ???? ?? 0? suba (opr) subtract memory from a a ? m ? aaimm adir aext aind,x aind,y 80 90 b0 a0 18 a0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subb (opr) subtract memory from b b ? m ? baimm adir aext aind,x aind,y c0 d0 f0 e0 18 e0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subd (opr) subtract memory from d d ? m : m + 1 ? dimm dir ext ind,x ind,y 83 93 b3 a3 18 a3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? swi software interrupt see figure 3-2 inh 3f ? 14 ??? 1 ???? tab transfer a to b a ? b inh 16 ? 2 ???? ?? 0? tap transfer a to cc register a ? ccr inh 06 ? 2 ??????? tba transfer b to a b ? a inh 17 ? 2 ???? ?? 0? test test (only in test modes) address bus counts inh 00 ? * ? ? ? ? ? ? ? ? tpa transfer cc register to a ccr ? a inh 07 ? 2 ???????? table 3-2. instruction set (sheet 7 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc711d3 ? rev. 2 50 central processor unit (cpu) motorola tst (opr) test for zero or minus m ? 0 ext ind,x ind,y 7d 6d 18 6d hh ll ff ff 6 6 7 ???? ?? 00 tsta test a for zero or minus a ? 0 a inh 4d ? 2 ? ? ? ? ?? 00 tstb test b for zero or minus b ? 0 b inh 5d ? 2 ? ? ? ? ?? 00 tsx transfer stack pointer to x sp + 1 ? ix inh 30 ? 3 ???????? tsy transfer stack pointer to y sp + 1 ? iy inh 18 30 ? 4 ???????? txs transfer x to stack pointer ix ? 1 ? sp inh 35 ? 3 ???????? tys transfer y to stack pointer iy ? 1 ? sp inh 18 35 ? 4 ???????? wai wait for interrupt stack regs & wait inh 3e ? ** ? ? ? ? ? ? ? ? xgdx exchange d with x ix ? d, d ? ix inh 8f ? 3 ???????? xgdy exchange d with y iy ? d, d ? iy inh 18 8f ? 4 ???????? table 3-2. instruction set (sheet 8 of 8) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c cycle * infinity or until reset occurs ** 12 cycles are used beginning with the opcode fetch. a wait stat e is entered which remains in effect for an integer number of mpu e-clock cycles (n) until an interrupt is recognized. finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). operands dd = 8-bit direct address ($0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) (is added to index) hh = high-order byte of 16-bit extended address ii = one byte of immediate data jj = high-order byte of 16-bit immediate data kk = low-order byte of 16-bit immediate data ll = low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = signed relative offset $80 (?128) to $7f (+127) (offset relative to address following machine code offset byte) operators ( ) contents of register shown inside parentheses ? is transferred to ? is pulled from stack ? is pushed onto stack boolean and + arithmetic addition symbol except where used as inclusive-or symbol in boolean formula exclusive-or ? multiply : concatenation ? arithmetic subtraction symbol or negation symbol (two?s complement) condition codes ? bit not changed 0 bit always cleared 1 bit always set ? bit cleared or set, depending on operation bit can be cleared, cannot become set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 51 data sheet ? mc68hc711d3 section 4. resets, interrupts, and low-power modes 4.1 introduction this section describes the internal and external resets and interrupts of the mc68hc711d3 and its two low power-consumption modes. 4.2 resets the microcontroller unit (mcu) can be reset in any of these four ways: 1. an active-low input to the reset pin 2. a power-on reset (por) function 3. a clock monitor failure 4. a computer operating properly (cop) watchdog timer timeout the reset input consists mainly of a schm itt trigger that senses the reset line logic level. 4.2.1 reset pin to request an external reset, the reset pin must be held low for at least eight e-clock cycles, or for one e-clock cycle if no distinction is needed between internal and external resets. 4.2.2 power-on reset (por) power-on reset occurs when a positive transition is detected on v dd . this reset is used strictly for power turn on conditions and should not be used to detect any drop in the power supply voltage. if the external reset pin is low at the end of the power-on delay time, the processor rema ins in the reset condition until reset goes high. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 52 resets, interrupts, and low-power modes motorola 4.2.3 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out unless it is serviced within a specific time by a pr ogram reset sequence. if the cop watchdog timer is allowed to timeout, a reset is generated, which drives the reset pin low to reset the mcu and the external system. in the mc68hc711d3, the cop reset function is enabled out of reset in normal modes. if the user does not want the co p enabled, he must write a 1 to the nocop bit of the configuration control regi ster (config) after reset. this bit is writable only once after reset in normal modes (see 2.3.3 configuration control register for more information). protected control bits (cr1 and cr0) in the configuration options register (option) allow the user to select one of the four cop timeout rates. table 4-1 shows the relationship between cr1 and cr0 and the cop timeout period for various system clock frequencies. the sequence for resetting the watchdog timer is: 1. write $55 to the cop reset register (coprst) to arm the cop timer clearing mechanism. 2. write $aa to the coprst register to clear the cop timer both writes must occur in this sequence prior to the timeout, but any number of instructions can be executed between the two writes. table 4-1. cop time out periods cr0 cr1 e 2 15 divided by xtal = 2 23 time out ?0/+15.6 ms xtal = 8.0 mhz time out ?0/+16.4 ms xtal = 4.9152 mhz time out ?0/+26.7 ms xtal = 4.0 mhz time out ?0/+32.8 ms xtal = 3.6864 mhz time out ?0/+35.6 ms 0 0 1 15.625 ms 16.384 ms 26.667 ms 32.768 ms 35.556 ms 0 1 4 62.5 ms 65.536 ms 106.67 ms 131.07 ms 142.22 ms 1 0 16 250 ms 262.14 ms 426.67 ms 524.29 ms 568.89 ms 1 1 64 1 sec 1.049 sec 1.707 sec 2.1 sec 2.276 ms e = 2.1 mhz 2.0 mhz 1.2288 mhz 1.0 mhz 921.6 khz address: $003a bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 figure 4-1. arm/reset cop timer circuitry register (coprst) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes resets mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 53 4.2.4 clock monitor reset the mcu contains a clock monitor circuit that measures the e-clock frequency. if the e-clock input rate is above approximately 200 khz, then the clock monitor does not generate an mcu reset. if the e-clock signal is lost or its frequency falls below 10 khz, then an mcu reset can be generated, and the reset pin is driven low to reset the external system. 4.2.5 system configuration options register the system configuration options register (option) is a special-purpose register with several time-protected bits. option is used during initialization to configure internal system options. bits 5, 4, 2, 1, and 0 can be written only once during the first 64 e-clock cycles after reset in normal modes (where the hprio regi ster bit (smod) is cleared). in special modes (where smod = 1), the bits can be written at any time. bit 3 can be written at anytime. bits 7, 6, and 2 ? not implemented always read 0. irqe ? irq edge/level sensitivity select this bit can be written only once during t he first 64 e-clock cycles after reset in normal modes. 1 = irq is configured to respond only to falling edges. 0 = irq is configured for low-level wired-or operation. dly ? stop mode exit turnon delay this bit is set during reset and can be written only once during the first 64 e-clock cycles after reset in normal modes . if an external clock source rather than a crystal is used, the stabilization delay can be inhibited because the clock source is assumed to be stable. 1 = a stabilization delay of 4064 e-cloc k cycles is imposed before processing resumes after a stop mode wakeup. 0 = no stabilization delay is imposed after story recovery. cme ? clock monitor enable 1 = clock monitor circuit is enabled. 0 = clock monitor circuit is disabled. address: $ 0 039 bit 7654321bit 0 read: 0 0 irqe dly cme 0 cr1 cr 0 write: reset:00010000 figure 4-2. system configuration options register (option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 54 resets, interrupts, and low-power modes motorola cr1 and cr0 ? cop timer rate selects the cop system is driven by a constant frequency of e 2 15 . these two bits specify an additional divide- by value to arrive at the cop timeout rate. these bits are cleared during reset and can be written only once during the first 64 e-clock cycles after reset in normal modes. the value of these bits is: 4.3 interrupts excluding reset-type interrupts, there are 17 hardware interrupts and one software interrupt that can be generated from all the possible sources. these interrupts can be divided into two categories: maskable and non-maskable. fifteen of the interrupts can be masked using the i bit of the condition code register (ccr). all the on-chip (hardware) interrupts are indi vidually maskable by local control bits. the software interrupt is non-maskable. the external input to the xirq pin is considered a non-maskable interrupt because it cannot be masked by software once it is enabled. however, it is masked during reset and upon receipt of an interrupt at the xirq pin. illegal opcode is al so a non-maskable interrupt. table 4-2 provides a list of the interrupts with a vector location in memory for each, as well as the actual condition code and control bits that mask each interrupt. figure 4-3 shows the interrupt stacking order. cr1 cr0 e 2 15 divided by 00 1 01 4 10 16 11 64 table 4-2. interrupt and reset vector assignments vector address interrupt source ccr mask local mask $ffc0, $ffc1 $ffd4, $ffd5 reserved ? ? $ffd6, $ffd7 sci serial system: ? sci transmit complete ? sci transmit data register empty ? sci idle line detect ? sci receiver overrun ? sci receive data register full i bit tcie tie ilie rie rie $ffd8, $ffd9 spi serial transfer complete i bit spie $ffda, $ffdb pulse accumulator input edge i bit paii $ffdc, $ffdd pulse accumulator overflow i bit paovi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes interrupts mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 55 figure 4-3. interrupt stacking order $ffde, $ffdf timer overflow i bit toi $ffe0, $ffe1 timer input captur e 4/output compare 5 i bit i4/o5i $ffe2, $ffe3 timer output compare 4 i bit oc4i $ffe4, $ffe5 timer output compare 3 i bit oc3i $ffe6, $ffe7 timer output compare 2 i bit oc2i $ffe8, $ffe9 timer output compare 1 i bit oc1i $ffea, $ffeb timer input capture 3 i bit ic3i $ffec, $ffed timer input capture 2 i bit ic2i $ffee, $ffef timer input capture 1 i bit ic1i $fff0, $fff1 real time interrupt i bit rtii $fff2, $fff3 irq (external pin) i bit none $fff4, $fff5 xirq pin (pseudo non-maskable) x bit none $fff6, $fff7 software interrupt none none $fff8, $fff9 illegal opcode trap none none $fffa, $fffb cop failure (reset) none nocop $fffc, $fffd clock monitor fail (reset) none cme $fffe, $ffff reset none none stack sp pcl ? sp before interrupt sp ? 1 pch sp ? 2 iyl sp ? 3 iyh sp ? 4 ixl sp ? 5 ixh sp ? 6 acca sp ? 7 accb sp ? 8 ccr sp ? 9 ? sp after interrupt table 4-2. interrupt and reset vector assignments (continued) vector address interrupt source ccr mask local mask f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 56 resets, interrupts, and low-power modes motorola 4.3.1 software interrupt (swi) the swi is executed the same as any other instruction and takes precedence over interrupts only if the other interrupts are masked (with i and x bits in the ccr set). swi execution is similar to that of the ma skable interrupts in that it sets the i bit, stacks the central processor unit (cpu) registers, etc. note: the swi instruction cannot be executed as long as another interrupt is pending. however, once the swi instruction has begun, no other interrupt can be honored until the first instruction in the swi service routine is completed. 4.3.2 illegal opcode trap since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit has been included in the mcu. when an illegal opcode is detected, an interrupt is required to t he illegal opcode vector. the illegal opcode vector should never be left uninitialized. 4.3.3 real-time interrupt (rti) the real-time interrupt (rti) provides a programmable periodic interrupt. this interrupt is maskable by either the i bit in the ccr or the rti enable (rtii) bit of the timer interrupt mask register 2 (tmsk2). the rate is based on the mcu e clock and is software selectable to the e 2 13 , e 2 14 , e 2 15 , or e 2 16 . see pactl, tmsk2, and tflg2 register descriptions in section 8. programmable timer for control and status bit information. 4.3.4 interrupt mask bits in the ccr upon reset, both the x bit and i bit of the ccr are set to inhibit all maskable interrupts and xirq. after minimum system initialization, software may clear the x bit by a tap instruction, thus enabling xirq interrupts. thereafter software cannot set the x bit. so, an xirq interrupt is effectively a non-maskable interrupt. since the operation of the i bit related interrupt structure has no effect on the x bit, the internal xirq pin remains effectively non-masked. in the interrupt priority logic, the xirq interrupt is a higher priority than any source that is mask able by the i bit. all i bit related interrupts operate normally with their own priority relationship. when an i bit related interrupt occurs, the i bit is automatically set by hardware after stacking the ccr byte. the x bit is not a ffected. when an x bit related interrupt occurs, both the x and the i bit are automatic ally set by hardware after stacking the ccr. a return-from-interrupt (rti) instruct ion restores the x and i bits to their preinterrupt request state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes interrupts mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 57 4.3.5 priority structure interrupts obey a fixed hardware priority circuit to resolve simultaneous requests. however one i bit related interrupt source may be elevated to the highest i bit priority in the resolution circuit. six interrupt sources are not masked by the i bit in the ccr and have these fixed priority relationships: 1. reset 2. clock monitor failure 3. cop failure 4. illegal opcode 5. swi 6. xirq swi is actually an instruction and has highes t priority, other than resets, in that once the swi opcode is fetched, no other interrupt can be honored until the swi vector has been fetched. each of the previous sources is an input to the priority resolution circuit. the highest i bit masked priority input to th e resolution circuit is assigned to be connected to any one of the remaining i bit related interrupt sources. this assignment is made under the software cont rol of the hprio register. to avoid timing races, the hprio register can be written only while the i bit related interrupts are inhibited (i bit of ccr is logic 1). an interrupt that is assigned to this higher priority position is still subject to masking by any associated control bits or by the i bit in the ccr. the interrupt vector address is not affected by assigning a source to the higher priority position. figure 4-4 , figure 4-5 , and figure 4-6 illustrate the interrupt process as it relates to normal processing. figure 4-4 shows how the cpu begins from a reset, and how interrupt detection relates to normal opcode fetches. figure 4-5 is an expansion of a block in figure 4-4 and shows how interrupt priority is resolved. figure 4-6 is an expansion of the sci interrupt block of figure 4-4 and shows the resolution of interrupt source s within the sci subsystem. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 58 resets, interrupts, and low-power modes motorola figure 4-4. processing flow out of reset (sheet 1 of 2) 2a bit x in y n xirq y n pin low? ccr = 1? begin instruction sequence 1a stack cpu registers set bits i and x fetch vector $fff4, $fff5 set bits s , i , and x reset mcu hardware power-on reset (por) external reset clock monitor fail (with cme = 1) cop watchdog timeout (with nocop = 0) delay 4064 e cycles load program counter with contents of $fffe, $ffff (vector fetch) load program counter with contents of $fffc, $fffd (vector fetch) load program counter with contents of $fffa, $fffb (vector fetch) highest priority lowest priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes interrupts mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 59 figure 6-3. processing flow ou t of reset (s heet 2 of 2) i bit in ccr set? 2a y n any i-bit interrupt y n pending? fetch opcode illegal opcode? n y wai y n instruction? swi instruction? y n rti instruction? y n execute this instruction stack cpu registers n y interrupt yet? set i bit stack cpu registers set i bit fetch vector $fff8, $fff9 stack cpu registers fetch vector $fff6, $fff7 restore cpu registers from stack 1a stack cpu registers resolve interrupt priority and fetch vector for highest pending source see figure 4-5 set i bit start next instruction sequence f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 60 resets, interrupts, and low-power modes motorola figure 4-5. interrupt priority resolution (sheet 1 of 2) 2a begin set x bit fetch vector $fff4, $fff5 x bit in ccr set ? y n xirq pin low ? y n highest priority interrupt ? y n irq ? y n fetch vector $fff2, $fff3 fetch vector $fff0, $fff1 rtii = 1 ? y n real-time interrupt ? y n fetch vector $ffee, $ffef ic1i = 1 ? y n timer ic1f ? y n fetch vector $ffec, $ffed ic2i = 1 ? y n timer ic2f ? y n fetch vector $ffea, $ffeb ic3i = 1 ? y n timer ic3f ? y n fetch vector $ffe8, $ffe9 oc1i = 1 ? y n timer oc1f ? y n 2b fetch vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes interrupts mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 61 figure 5-6. interrupt priori ty resolution (sheet 2 of 2) toi = 1? y n y n paovi = 1? paii = 1? y n spie = 1? y n y n flag y n y n flag flag y n flags y n paif = 1? spif = 1? or tof = 1? paovf = 1 fetch vector $ffde, $ffdf fetch vector $ffdc, $ffdd fetch vector $ffda, $ffdb fetch vector $ffd6, $ffd7 fetch vector $ffd8, $ffd9 oc2i = 1? y n y n oc3i = 1? oc4i = 1? y n oc5i = 1? y n flag y n y n flag flag y n flag y n oc4f = 1? oc5f = 1? oc2f = 1? oc3f = 1 fetch vector $ffe6, $ffe7 fetch vector $ffe4, $ffe5 fetch vector $ffe2, $ffe3 fetch vector $ffe0, $ffe1 modf = 1? 2a 2b end fetch vector $fff2, $fff3 sci interrupt? see figure 4-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 62 resets, interrupts, and low-power modes motorola figure 4-6. interrupt source resolution within sci flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? no valid sci request yes valid sci request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes interrupts mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 63 4.3.6 highest priority i interrupt and miscellaneous register (hprio) four bits of this register (psel3?psel0) are used to select one of the i bit related interrupt sources and to elevate it to the hi ghest i bit masked position of the priority resolution circuit. in addition, four miscel laneous system control bits are included in this register. rboot ? read bootstrap rom this bit can be read at any time. it can be written only in special modes (smod = 1). in special bootstrap mode, it is set during reset. reset clears it in all other modes. 1 = bootloader rom is enabled in the memory map at $bf00?$bfff. 0 = bootloader rom is disabled and is not in the memory map. smod and mda ? special mode select and mode select a these two bits can be read at any time.these bits reflect the status of the moda and modb input pins at the rising edge of reset. smod may be written only in special modes. it cannot be written to a 1 after being cleared without an interim reset. mda may be written at any time in special modes, but only once in normal modes. an interpretation of the values of these two bits is shown in table 4-3 . address: $ 0 03c bit 7654321bit 0 read: rboot smod mda irvne psel3 psel2 psel1 psel0 write: reset: note 1 0101 1. the values of the rboot, smod, irvne, and mda bits at reset depend on the mode during initialization. refer to table 4-3 . figure 4-7. highest priority i-bit interrupt and miscellaneous register (hprio) table 4-3. hardware mode select summary inputs mode latched at reset modb moda smod mda 10 single chip 00 1 1 expanded multiplexed 0 1 0 0 special bootstrap 1 0 0 1 special test 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 64 resets, interrupts, and low-power modes motorola irvne ? internal read visibility/not e this bit may be read at any time. it may be written once in any mode. irvne is set during reset in special test mode only, and cleared by reset in the other modes. 1 = data from internal reads is driven out on the external data bus in expanded modes. 0 = data from internal reads is not visible on the external data bus. as shown in the table, in single-chip and bootstrap modes irvne determines whether the e clock is driven out or forced low. 1 = e pin driven low 0 = e clock driven out of the chip note: to prevent bus conflicts, when using inter nal read visibility, the user must disable all external devices from driving the data bus during any internal access. psel3?psel0 ? priority selects these four bits are used to specify one i bit related interrupt source, which then becomes the highest priority i bit related interrupt source. these bits may be written only while the i bit in the ccr is se t, inhibiting i bit related interrupts. an interpretation of the value of these bits is shown in table 4-4 . during reset, psel3?psel0 are initialized to 0101, which corresponds to reserved (default to irq ). irq becomes the highest priority i bit related interrupt source. mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne may be written single chip 0 on off e once expanded multiplexed 0 on off irv once bootstrap 0 on off e once special test 1 on on irv once table 4-4. highest priority interrupt selection psel3?psel0 interrupt source promoted 0 0 0 0 timer overflow 0 0 0 1 pulse accumulator overflow 0 0 1 0 pulse accumulator input edge 0 0 1 1 spi serial transfer complete 0 1 0 0 sci serial system 0 1 0 1 reserved (default to irq ) 0 1 1 0 irq (external pin) 0 1 1 1 real-time interrupt 1 0 0 0 timer input capture 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes low-power operation mc68hc711d3 ? rev. 2 data sheet motorola resets, interrupts, and low-power modes 65 4.4 low-power operation the m68hc11 family of microcontroller units (mcu) has two programmable low power-consumption modes: stop and wait. in the wait mode, the on-chip oscillator remains active. in the stop mode, the oscillator is stopped. this subsection describes these two low power-consumption modes. 4.4.1 stop mode the stop instruction places the mcu in its lowest power-consumption mode, provided the s bit in the ccr is cleared. in this mode, all clocks are stopped, thereby halting all internal processing. to exit the stop mode, a low level must be applied to either the irq , xirq , or reset pin. an external interrupt used at irq is only effective if the i bit in the ccr is cleared. an external interrupt applied at the xirq input is effective, regardless of the setting of the x bit of the ccr. however, the actual recovery sequence differs, depending on the x bit setting. if the x bit is cleared, the mcu starts with the stacking sequence leading to t he normal service of the xirq request. if the x bit is set, the processi ng always continues with th e instruction immediately following the stop instruction. a low input to the reset pin always results in an exit from the stop mode, and the start of mcu operations is determined by the reset vector. the cpu will not exit stop mode correctly when interrupted by irq or xirq if the instruction preceding stop is a column 4 or 5 accumulator inherent (opcodes $4x and $5x) instruction, such as nega, negb, coma, comb, etc. these single-byte, two-cycle instructions must be followed by an nop, then the stop command. if reset is used to exit st op mode, the cpu will respond properly. a restart delay is required if the internal oscillator is being used. the delay allows the oscillator to stabilize when exiting the stop mode. if a stable external oscillator is being used, the delay (dly) bit in the option register can be cleared to bypass the delay. if the dly bit is clear, the reset pin would not normally be used to exit the stop mode. the reset sequence sets the dly bit, and the restart delay would be reimposed. 1 0 0 1 timer input capture 2 1 0 1 0 timer input capture 3 1 0 1 1 timer output compare 1 1 1 0 0 timer output compare 2 1 1 0 1 timer output compare 3 1 1 1 0 timer output compare 4 1 1 1 1 timer input capt ure 4/output compare 5 table 4-4. highest priority interrupt selection (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets, interrupts, and low-power modes data sheet mc68hc711d3 ? rev. 2 66 resets, interrupts, and low-power modes motorola 4.4.2 wait mode the wait (wai) instruction places the mcu in a low power-consumption mode. the wait mode consumes more power than t he stop mode since the oscillator is kept running. upon execution of the wai instru ction, the machine state is stacked and program execution stops. the wait state can be exited only by an unmasked interrupt or reset . if the i bit of the ccr is set and the cop is disabled , the timer system is turned off by wai to further reduce power consumption. the amount of power savings is application dependent. it also depends upon the circuitry connected to the mcu pins, and upon subsystems such as the timer, serial peripheral interface (spi), or serial communications interface (sci) that were or were not active when the wait mode was entered. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola input/output (i/o) ports 67 data sheet ? mc68hc711d3 section 5. input/output (i/o) ports 5.1 introduction the mc68hc711d3 has four 8-bit input/output (i/o) ports; a, b, c, and d. in the 40-pin version, port a bits 4 and 6 are no t bonded. port functions are controlled by the particular mode of operation selected, as shown in table 1-1. port signal functions . in the single-chip and bootstrap modes, al l the ports are configured as parallel input/output (i/o) data ports. in expanded multiplexed and test modes, ports b, c, and lines d6 (as) and d7 (r/w ) are configured as a memory expansion bus, with: port b as the high-order address bus port c as the multiplexed address and data bus as as the demultiplexing signal r/w as data bus direction control the remaining ports are unaffected by mode changes. ports a and d can be used as general-purpose i/o ports, though each has an alternate function. port a bits handle the timer functions. port d handles serial peripheral interface (spi) and serial communications interface (sci) functions in addition to its bus direction control functions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc711d3 ? rev. 2 68 input/output (i/o) ports motorola 5.2 port a port a shares functions with the timer system and has: three input only pins three output only pins two bidirectional i/o pins pins pa6 and pa4 are not bonded in the 40-pin dual in-line package (dip), and their oc output functions are unavailable, but their software interrupts are available. porta can be read any time. inputs return the pin level, whereas outputs return the pin driver input level. if written, port a stores the data in an internal latch. it drives the pins only if they are configured as outputs. writes to porta do not change the pin state when the pins are configured for timer output compares. out of reset, port a bits 7 and 3?0 are general high-impedance inputs, while bits 6?4 are outputs, driving low. on bidirectional lines pa7 and pa3, the timer forces the i/o state to be an output if the associated output compare is enabled. in this case, the data direction bits ddra7 and ddra3 in pactl will not be changed or have any effect on those bits. when the output compare functions associated with these pins are disabled, the ddr bits in pactl govern the i/o state. address: $ 0 000 bit 7654321bit 0 read: pa7 pa6 (1) pa5 pa4 (1) pa3 pa2 pa1 pa0 write: reset: hi-z 0 0 0 hi-z hi-z hi-z hi-z alt. func.: and/or: pai oc1 oc2 oc1 oc3 oc1 oc4 oc1 ic4/oc5 oc1 ic1 ? ic2 ? ic3 ? 1. this pin is not bonded in the 40-pin version. figure 5-1. port a data register (porta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68hc711d3 ? rev. 2 data sheet motorola input/output (i/o) ports 69 5.3 port b port b is an 8-bit, general-purpose i/o port with a data register (portb) and a data direction register (ddrb). in the single-chip mode, port b pins are general-purpose i/o pins (pb7?pb0). in the expanded-multiplexed mode, all of the port b pins act as the high-order address bits (a15?a8) of the address bus. 5.3.1 port b data register portb can be read at any time. inputs return the sensed levels at the pin, while outputs return the input level of the port b pin drivers. if portb is written, the data is stored in an internal latch and can be driven only if port b is configured for general-purpose outputs in single-chip or bootstrap mode. port b pins are general--purpose inputs out of reset in single-chip and bootstrap modes. these pins are outputs (the high -order address bits) out of reset in expanded multiplexed and test modes. 5.3.2 port b data direction register ddb7?ddb0 ? data direction bits for port b 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured for input only address: $ 0 004 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset:00000000 alt. func.: a15 a14 a13 a12 a11 a10 a9 a8 figure 5-2. port b data register (portb) address: $ 0 006 bit 7654321bit 0 read: ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 write: reset:00000000 figure 5-3. data direction register for port b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc711d3 ? rev. 2 70 input/output (i/o) ports motorola 5.4 port c port c is an 8-bit, general-purpose i/o port with a data register (portc) and a data direction register (ddrc). in the single-ch ip mode, port c pins are general-purpose i/o pins (pc7?pc0). in the expanded-multiplexed mode, port c pins are configured as multiplexed address/data pins. during the address cycle, bits 7?0 of the address are output on pc7?pc0. during the data cycle, bits 7?0 (pc7?pc0) are bidirectional data pins controlled by the r/w signal. 5.4.1 port c control register cwom ? port c wire-or mode bit 1 = port c outputs are open drain (to facilitate testing) 0 = port c operates normally 5.4.2 port c data register portc can be read at any time. inputs return the sensed levels at the pin, while outputs return the input level of the port c pin drivers. if portc is written, the data is stored in an internal latch and can be driven only if port c is configured for general-purpose outputs in single-chip or bootstrap mode. port c pins are general-purpose inputs out of reset in single-chip and bootstrap modes. these pins are multiplexed low-or der address and data bus lines out of reset in expanded-multiplexed and test modes. address: $ 0 002 bit 7654321bit 0 read: 00cwom00000 write: reset:00000000 figure 5-4. port c control register (pioc) address: $ 0 003 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset:00000000 figure 5-5. port c data register (portc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68hc711d3 ? rev. 2 data sheet motorola input/output (i/o) ports 71 5.4.3 port c data direction register ddc7?ddc0 ? data direction bits for port c 1 = corresponding port c pin is configured as output 0 = corresponding port c pin is configured for input only 5.5 port d port d is an 8-bit, general-purpose i/o port with a data register (portd) and a data direction register (ddrd). the eigh t port d bits (d7?d0) can be used for general-purpose i/o, for the serial comm unications interface (sci) and serial peripheral interface (spi) subsystems, or for bus data direction control 5.5.1 port d data register portd can be read at any time and inputs return the sensed levels at the pin; whereas, outputs return the input level of the port d pin drivers. if portd is written, the data is stored in an internal latch, and can be driven only if port d is configured as general-purpose output. this port shares functions with the on-chip sci and spi subsystems, while bits 6 and 7 control t he direction of data flow on the bus in expanded and special test modes. address: $ 0 007 bit 7654321bit 0 read: ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 write: reset:00000000 figure 5-6. data direction register for port c (ddrc) address: $ 0 008 bit 7654321bit 0 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 figure 5-7. port d data register (portd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc711d3 ? rev. 2 72 input/output (i/o) ports motorola 5.5.2 port d data direction register ddd7?ddd0 ? data direction for port d when port d is a general-purpose i/o po rt, the ddrd register controls the direction of the i/o pins as follows: 0 = configures the corresponding port d pin for input only 1 = configures the corresponding port d pin for output in expanded and test modes, bits 6 and 7 are dedicated as and r/w . when port d is functioning with the spi system enabled, bit 5 is dedicated as the slave select (ss ) input. in spi slave mode, ddd5 has no meaning or effect. in spi master mode, ddd5 affects port d bit 5 as follows: 0 = port d bit 5 is an error-detect input to the spi. 1 = port d bit 5 is configured as a general-purpose output line. if the spi is enabled and expects port d bits 2, 3, and 4 (miso, mosi, and sck) to be inputs, then they are inputs, regardl ess of the state of ddrd bits 2, 3, and 4. if the spi expects port d bits 2, 3, and 4 to be outputs, they are outputs only if ddrd bits 2, 3, and 4 are set. address: $ 0 009 bit 7654321bit 0 read: ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 write: reset:00000000 figure 5-8. data direction register for port d (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 73 data sheet ? mc68hc711d3 section 6. serial commun ications inte rface (sci) 6.1 introduction the serial communications interface (sci) is a universal asynchronous receiver transmitter (uart), one of two independent se rial input/output (i/o) subsystems in the mc68hc711d3. it has a standard non-return to zero (nrz) format (one start, eight or nine data, and one stop bit). several baud rates are available. the sci transmitter and receiver are independent, but use the same data format and bit rate. 6.2 data format the serial data format requires these conditions: an idle line in the high state before transmission or reception of a message a start bit, logic 0, transmitted or rece ived, that indicates the start of each character data that is transmitted and receiv ed least significant bit (lsb) first a stop bit, logic 1, used to indicate t he end of a frame. a frame consists of a start bit, a character of eight or nine data bits, and a stop bit. a break, defined as the transmission or reception of a logic 0 for some multiple number of frames selection of the word length is controlled by the m bit in the sci control register 1 (sccr1). 6.3 transmit operation the sci transmitter includes a parallel tr ansmit data register (scdr) and a serial shift register that puts data from the scdr into serial form. the contents of the serial shift register can only be writt en through the scdr. this double-buffered operation allows a character to be shifted out serially while another character is waiting in the scdr to be transferred into the serial shift register. the output of the serial shift register is applied to pd1 as long as transmission is in progress or the transmit enable (te) bit of serial communication contro l register 2 (sccr2) is set. the block diagram, figure 6-1 , shows the transmit serial shift register and the buffer logic at the top of the figure. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 74 serial communications interface (sci) motorola figure 6-1. sci transmitter block diagram fe nf or idle rdrf tc tdre scsr interrupt status sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd scdr tx buffer transfer tx buffer shift enable jam enable preamble?jam 1s break?jam 0s (write only) force pin direction (out) size 8/9 wake m t8 r8 sccr1 sci control 1 transmitter baud rate clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) receive operation mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 75 6.4 receive operation during receive operations, the transmit s equence is reversed. the serial shift register receives data and transfers it to a parallel receive data register (scdr) as a complete word. refer to figure 6-2 . this double-buffered operation allows a character to be shifted in serially while another characte r is already in the scdr. an advanced data recovery scheme disti nguishes valid data from noise in the serial data stream. the data input is sele ctively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. 6.5 wakeup feature the wakeup feature reduces sci service overhead in multiple receiver systems. software for each receiver evaluates the first character of each message. the receiver is placed in wakeup mode by wr iting a 1 to the rwu bit in the sccr2 register. while rwu is 1, all of the rece iver-related status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). although rwu can be cleared by a software write to sccr2, to do so wo uld be unusual. normally, rwu is set by software and is cleared automatically with hardware. whenever a new message begins, logic alerts the sleeping receivers to wake up and evaluate the initial character of the new message. two methods of wakeup are available: idle line wakeup address mark wakeup during idle line wakeup, a sleeping rece iver awakens as soon as the rxd line becomes idle. in the address mark wakeup, l ogic 1 in the most significant bit (msb) of a character wakes up all sleeping receivers. 6.5.1 idle-line wakeup to use the receiver wakeup method, es tablish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of receivers. this addressing sc heme can take any form as long as all transmitting and receiving devices ar e programmed to understand the same scheme. because the addressing informati on is usually the first frame(s) in a message, receivers that are not part of the current task do not become burdened with the entire set of addressing frames. all receivers are awake (rwu = 0) when each message begins. as soon as a receiver determines that the message is not intended for it, software sets the rwu bit (rwu = 1), which inhibits further flag setting until the rxd line goes idle at the end of the message. as soon as an idle line is detected by receiver logic, hardware automatically clears the rwu bit so that the first frame of the next message can be received. this type of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time between frames in a message. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 76 serial communications interface (sci) motorola figure 6-2. sci receiver block diagram fe nf or idle rdrf tc tdre scsr sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m t8 r8 wakeup logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0 rxd scdr rx buffer stop (8)76543210 10 (11) - bit rx shift register (read only) sccr1 sci control 1 rie rdrf start msb all 1s data recovery 16 rwu re m disable driver 16x baud rate clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci error detection mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 77 6.5.2 address-mark wakeup the serial characters in this type of wakeup consist of seven (eight if m = 1) information bits and an msb, which indicates an address character (when set to 1 ? mark). the first character of each message is an addressing character (msb = 1). all receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver. as soon as a receiver determines that a message is not intended for it, the receiver activates the rwu function by using a software write to set the rwu bit. because setting rwu inhibits receiver-rela ted flags, there is no further so ftware overhead for the rest of this message. when the next message begins, its first character has its msb set, which automatically clears the rwu bit and enables normal character reception. the first character whose msb is set is also the first c haracter to be received after wakeup because rwu gets cleared before the stop bit for that frame is serially received. this type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. 6.6 sci error detection three error conditions can occur during generation of sci system interrupts: serial communications data register (scdr) overrun received bit noise framing three bits (or, nf, and fe) in the serial communications status register (scsr) indicate if one of these error conditions exists. the overrun error (or) bit is set when the next byte is ready to be transferred from the receive shift register to the scdr and the scdr is already full (r drf bit is set). when an overrun error occurs, the data that caused the overrun is lost and the data that was already in scdr is not disturbed. the or is clear ed when the scsr is read (with or set), followed by a read of the scdr. the noise flag (nf) bit is set if there is noise on any of the received bits, including the start and stop bits. the nf bit is not set until the rdrf flag is set. the nf bit is cleared when the scsr is read (with fe equal to 1) followed by a read of the scdr. when no stop bit is detected in the received data character, the framing error (fe) bit is set. fe is set at the same time as the rdrf. if the byte received causes both framing and overrun errors, the processor only recognizes the overrun error. the framing error flag inhibits further transfer of data into the scdr until it is cleared. the fe bit is cleared when the scsr is read (with fe equal to 1) followed by a read of the scdr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 78 serial communications interface (sci) motorola 6.7 sci registers this subsection describes the five addressable registers in the sci. 6.7.1 sci data register the sci data register (scdr) is a parallel register that performs two functions. it is the receive data register when it is r ead, and the transmit data register when it is written. reads access the receive data bu ffer and writes access the transmit data buffer. receive and transmit are double buffered. 6.7.2 sci control register 1 the sci control register 1 (sccr1) provides the control bits that determine word length and select the method used for the wakeup feature. r8 ? receive data bit 8 if m bit is set, r8 stores the ninth bit in the receive data character. t8 ? transmit data bit 8 if m bit is set, t8 stores ninth bit in transmit data character. m ? mode bit the mode bit selects character format 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ? wakeup by address mark/idle bit 0 = wakeup by idle line recognition 1 = wakeup by address mark (most significant data bit set) address: $002f bit 7654321bit 0 read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: unaffected by reset figure 6-3. sci data register (scdr) address: $002c bit 7654321bit 0 read: r8 t8 0 m wake 0 0 0 write: reset:uu000000 u = unaffected figure 6-4. sci control register 1 (sccr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci registers mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 79 6.7.3 sci control register 2 the sci control register 2 (sccr2) provides the control bits that enable or disable individual sci functions. tie ? transmit interrupt enable bit 1 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ? transmit complete interrupt enable bit 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ? receiver interrupt enable bit 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ? idle line interrupt enable bit 1 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ? transmitter enable bit when te goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble. 0 = transmitter disabled 1 = transmitter enabled re ? receiver enable bit 0 = receiver disabled 1 = receiver enabled rwu ? receiver wakeup control bit 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ? send break bit at least one character time of break is queued and sent each time sbk is written to 1. more than one break may be sent if the transmitter is idle at the time the sbk bit is toggled on and off, as the baud rate clock edge could occur between writing the 1 and writing the 0 to sbk. 0 = break generator off 1 = break codes generated as long as sbk = 1 address: $002d bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 6-5. sci control register 2 (sccr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 80 serial communications interface (sci) motorola 6.7.4 sci status register the sci status register (scsr) provides inputs to the interrupt logic circuits for generation of the sci system interrupt. tdre ? transmit data register empty flag this flag is set when scdr is empty. cl ear the tdre flag by reading scsr with tdre set and then writing to scdr. 0 = scdr busy 1 = scdr empty tc ? transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr with tc set and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ? receive data register full flag this flag is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr with rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle ? idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes id le again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr with idle set and then reading scdr. 0 = rxd line active 1 = rxd line idle or ? overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr with or set and then reading scdr. 0 = no overrun 1 = overrun detected address: $002e bit 7654321bit 0 read: tdre tc rdrf idle or nf fe 0 write: reset:11000000 figure 6-6. sci status register (scsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci registers mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 81 nf ? noise error flag nf is set if majority sample logi c detects anything other than a unanimous decision. clear nf by reading scsr with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected fe ? framing error bit fe is set when a 0 is detected where a stop bit was expected. clear the fe flag by reading scsr with fe set and then reading scdr. 0 = stop bit detected 1 = zero detected 6.7.5 baud rate register the baud rate register (baud) is used to select different baud rates for the sci system. the scp1 and scp0 bits function as a prescaler for the scr2?scr0 bits. together, these five bits provide multiple baud rate combinations for a given crystal frequency. normally, this register is writ ten once during initialization. the prescaler is set to its fastest rate by default out of reset and can be changed at any time. refer to table 6-1 and table 6-2 for normal baud rate selections. tclr ? clear baud rate counters (test) rckb ? sci baud rate clock check (test) scp1 and scp0 ? sci baud rate prescaler select bits these two bits select a prescale factor for the sci baud rate generator that determines the highest possible baud rate. address: $002b bit 7654321bit 0 read: tclr 0 scp1 scp0 rckb scr2 scr1 scr0 write: reset:00000uuu u = unaffected figure 6-7. baud rate register (baud) table 6-1. baud rate prescale selects scp1 and scp0 divide internal clock by crystal frequency in mhz 4.0 mhz (baud) 8.0 mhz (baud) 10.0 mhz (baud) 12.0 mhz (baud) 0 0 1 62.50 k 125.0 k 156.25 k 187.5 k 0 1 3 20.83 k 41.67 k 52.08 k 62.5 k 1 0 4 15.625 k 31.25 k 38.4 k 46.88 k 1 1 13 4800 9600 12.02 k 14.42 k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 82 serial communications interface (sci) motorola scr2?scr0 ? sci baud rate select bits these three bits select receiver and tr ansmitter bit rate based on output from baud rate prescaler stage. the prescale bits, scp1 and scp0, determine the highest baud rate and the scr2?scr0 bits select an additional binary submultiple ( 1 , 2, 4 , through 128) of this highest baud rate. the result of these two dividers in series is the 16 x receiver baud rate clock. the scr2?scr0 bits are not affected by reset and can be changed at any time, although they should not be changed when any sci transfer is in progress. figure 6-8 illustrates the sci baud rate timing chain. the prescale select bits determine the highest baud rate. the rate select bits determine additional divide by two stages to arrive at the receiver timing (rt) clock rate. the baud rate clock is the result of dividing the rt clock by 16. table 6-2. baud rate selects scr2?scr0 divide prescaler by highest baud rate (prescaler output from table 6-1 ) 4800 9600 38.4 k 0 0 0 1 4800 9600 38.4 k 0 0 1 2 2400 4800 19.2 k 0 1 0 4 1200 2400 9600 0 1 1 8 600 1200 4800 1 0 0 16 300 600 2400 1 0 1 32 150 300 1200 1 1 0 64 ? 150 600 1 1 1 128 ? ? 300 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) status flags and interrupts mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 83 figure 6-8. sci baud rate diagram 6.8 status flags and interrupts the sci transmitter has two status fl ags. these status flags can be read by software (polled) to tell when the corre sponding condition exists. alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present. status flags are automatically set by hardware logic conditions, but must be cleared by software, which provides an interlock me chanism that enables logic to know when software has noticed the status indication. the software clearing sequence for these flags is automatic ? functions that are normally performed in response to the status flags also satisfy the condi tions of the clearing sequence. 3 4 13 oscillator and clock generator ( 4) xtal extal e as internal bus clock (ph2) 1:1 scp1 and scp0 1:0 0:1 0:0 2 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 1:1:1 16 sci receive baud rate (16x) scr2?scr0 sci transmit baud rate (1x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 84 serial communications interface (sci) motorola tdre and tc flags are normally set when the transmitter is first enabled (te set to 1). the tdre flag indicates there is r oom in the transmit queue to store another data character in the tdr. the tie bit is the local interrupt mask for tdre. when tie is 0, tdre must be polled. when tie and tdre are 1, an interrupt is requested. the tc flag indicates the transmitter has completed the queue. the tcie bit is the local interrupt mask for tc. when tcie is 0, tc must be polled; when tcie is 1 and tc is 1, an interrupt is requested. writing a 0 to te requests that the transmitter stop when it can. the transmitter completes any transmission in progress bef ore actually shutting down. only an mcu reset can cause the transmitter to st op and shut down immediately. if te is written to 0 when the transmitter is already idle, the pin reverts to its general-purpose i/o function (synchronized to the bit-rate clock). if anything is being transmitted when te is written to 0, that character is completed before the pin reverts to general-purpose i/o, but any ot her characters waiting in the transmit queue are lost. the tc and tdre flags are set at the completion of this last character, even though te has been disabled. the sci receiver has five status flags, three of which can generate interrupt requests. the status flags are set by the sc i logic in response to specific conditions in the receiver. these flags can be read (pol led) at any time by software. refer to figure 6-9 , which shows sci interrupt arbitration. when an overrun takes place, the new character is lost, and the character that was in its way in the parallel rdr is undistur bed. rdrf is set when a character has been received and transferred in to the parallel rdr. the or flag is set instead of rdrf if overrun occurs. a new character is ready to be transferred into rdr before a previous character is read from rdr. the nf and fe flags provide additional information about the character in the rdr, but do not generate interrupt requests. the last receiver status flag and interrupt source come from the idle flag. the rxd line is idle if it has constantly been at logi c 1 for a full character time. the idle flag is set only after the rxd line has been busy and becomes idle, which prevents repeated interrupts for the whole time rxd remains idle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) status flags and interrupts mc68hc711d3 ? rev. 2 data sheet motorola serial communications interface (sci) 85 figure 6-9. interrupt source resolution within sci flag y n or = 1? y n y n tdre = 1? tc = 1? y n idle = 1? y n y n y n y n ilie = 1? rie = 1? tie = 1? begin re = 1? y n y n te = 1? tcie = 1? y n re = 1? y n rdrf = 1? valid sci request no valid sci request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) data sheet mc68hc711d3 ? rev. 2 86 serial communications interface (sci) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola serial peripheral interface (spi) 87 data sheet ? mc68hc711d3 section 7. serial peri pheral interface (spi) 7.1 introduction the serial peripheral interface (spi), an independent serial communications subsystem, allows the microcontroller unit (mcu) to communicate synchronously with peripheral devices, such as: transistor-transistor logi c (ttl) shift registers liquid crystal diode (lcd) display drivers analog-to-digital converter (adc) subsystems other microprocessors (mcus) the spi is also capable of inter-processor communication in a multiple master system. the spi system can be configured as either a master or a slave device with data rates as high as one half of t he e-clock rate when configured as master, and as fast as the e-clock rate when configured as slave. 7.2 functional description the central element in the spi system is the block containing the shift register and the read data buffer. the system is singl e buffered in the transmit direction and double buffered in the receive direction. this means that new data for transmission cannot be written to the shifter until the previous transfer is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. as long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition occurs. a single mcu register address is used for reading data from the read data buffer, and for writing data to the shifter. the spi status block represents the spi status functions (transfer complete, write collision, and mode fault) performed by the se rial peripheral status register (spsr). the spi control block represents those fu nctions that control the spi system through the serial peripheral control register (spcr). refer to figure 7-1 , which shows the spi block diagram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) data sheet mc68hc711d3 ? rev. 2 88 serial peripheral interface (spi) motorola figure 7-1. spi block diagram 7.3 spi transfer formats during an spi transfer, data is simultaneously transmitted and received. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows i ndividual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the select line can opt ionally be used to i ndicate a multiple master bus contention. refer to figure 7-2 . spr0 spr1 cpol cpha mstr dwom spe spie spi control register modf wcol spif spi status register 8-bit shift register read data buffer msb lsb internal data bus spi interrupt request mstr spe mstr dwom spe spr0 spi clock (master) spi control select divider ph2 (internal) clock logic clock pin control logic s m m s s m miso pd2 mosi pd3 sck pd4 ss pd5 spr1 2 4 16 32 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) clock phase and polarity controls mc68hc711d3 ? rev. 2 data sheet motorola serial peripheral interface (spi) 89 figure 7-2. spi transfer format 7.4 clock phase and polarity controls software can select one of four combinat ions of serial clock phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or active low clock, and has no significant effect on the transfer format. t he clock phase (cpha) control bit selects one of two different transfer formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. when cpha equals 0, the slave select (ss ) line must be negated and reasserted between each successive serial byte. also, if the slave writes data to the spi data register (spdr) while ss is active low, a write collision error results. when cpha equals 1, the ss line can remain low betw een successive transfers. 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb 1 2 3 5 4 slave cpha=1 transfer in progress master transfer in progress slave cpha=0 transfer in progress 1. ss asserted 2. master writes to spdr 3. first sck edge 4. spif set 5. ss negated sample input data out (cpha = 0) sample input data out (cpha = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) data sheet mc68hc711d3 ? rev. 2 90 serial peripheral interface (spi) motorola 7.5 spi signals this subsection contai ns description of the four spi signals: master in/slave out (miso) master out/slave in (mosi) serial clock (sck) slave select (ss ) 7.5.1 master in/slave out (miso) miso is one of two unidirectional serial data signals. it is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. 7.5.2 master out/slave in (mosi) the mosi line is the second of the two unid irectional serial data signals. it is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. 7.5.3 serial clock (sck) sck, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the mosi and miso lines. master and slave devices are capabl e of exchanging a byte of information during a sequence of eight clock cycles. four possible timing relationships can be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the spi clock rate select bits, spr1 and spr0, in the spcr of the master device, select the clock rate. in a slave device, spr1 and spr0 have no effect on the operation of the spi. 7.5.4 slave select (ss ) the ss input of a slave device must be externally asserted before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. if it goes low, a mode fault error flag (modf) is set in the serial peripheral st atus register (spsr). to disable the mode fault circuit, write a 1 in bit 5 of the port d data direction register. this sets the ss pin to act as a general-purpose output. the other three lines are dedicated to the spi whenever the serial peripheral interface is on. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi system errors mc68hc711d3 ? rev. 2 data sheet motorola serial peripheral interface (spi) 91 the state of the master and slave cpha bits affects the operation of ss . cpha settings should be identical for master and slave. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss can be left low between successive spi characters. in cases where there is only one spi slave mcu, its ss line can be tied to v ss as long as only cpha = 1 clock mode is used. 7.6 spi system errors two system errors can be detected by the sp i system. the first type of error arises in a multiple-master system when more than one spi device simultaneously tries to be a master. this error is called a mode fault. the second type of error, write collision, indicates that an attempt was made to write data to the spdr while a transfer was in progress. when the spi system is configured as a master and the ss input line goes to active low, a mode fault error has occurred ? usually because two devices have attempted to act as master at the same time. in cases where more than one device is concurrently configured as a master, there is a chance of contention between two pin drivers. for push-pull cmos driv ers, this contention can cause permanent damage. the mode fault attempts to protect the device by disabling the drivers. the mstr control bit in the spcr and all four ddrd control bits associated with the spi are cleared. an interrupt is generated subject to masking by the spie control bit and the i bit in the ccr. other precautions may need to be taken to prevent driver damage. if two devices are made masters at the same time, mode fault does not help protect either one unless one of them selects the other as slave. the amount of damage possible depends on the length of time both devices attempt to act as master. a write collision error occurs if the spdr is written while a transfer is in progress. because the spdr is not double buffered in the transmit direction, writes to spdr cause data to be written directly into the spi shift register. because this write corrupts any transfer in progress, a write collision error is generated. the transfer continues undisturbed, and the write data that caused the error is not written to the shifter. a write collision is normally a slave erro r because a slave has no control over when a master initiates a transfer. a master knows when a transfer is in progress, so there is no reason for a master to generate a write-collision error, although the spi logic can detect write collisions in both master and slave devices. the spi configuration determines the charac teristics of a transfer in progress. for a master, a transfer begins when data is written to spdr and ends when spif is set. for a slave with cpha equal to zero, a transfer starts when ss goes low and ends when ss returns high. in this case, spif is set at the middle of the eighth sck cycle when data is transferred from the sh ifter to the parallel data register, but the transfer is still in progress until ss goes high. for a slave with cpha equal to one, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) data sheet mc68hc711d3 ? rev. 2 92 serial peripheral interface (spi) motorola transfer begins when the sck line goes to its active level, which is the edge at the beginning of the first sck cycle. the transf er ends in a slave in which cpha equals one when spif is set. for a slave, after a byte transfer, sck must be in inactive state for at least 2 e-clock cycles before the next byte transfer begins. 7.7 spi registers the three spi registers, spcr, spsr, and spdr, provide control, status, and data storage functions. this sub-section provides a description of how these registers are organized. 7.7.1 spi control register spie ? serial peripheral interrupt enable bit 0 = spi interrupt disabled 1 = spi interrupt enabled spe ? serial peripheral system enable bit 0 = spi off 1 = spi on dwom ? port d wired-or mode bit dwom affects all six port d pins. 0 = normal cmos outputs 1 = open-drain outputs mstr ? master mode select bit 0 = slave mode 1 = master mode cpol ? clock polarity bit when the clock polarity bit is cleared and data is not being transferred, the sck pin of the master device has a steady state low value. when cpol is set, sck idles high. refer to figure 7-2 and 7.4 clock phase and polarity controls . cpha ? clock phase bit the clock phase bit, in conjunction with t he cpol bit, controls the clock-data relationship between master and slave. the cpha bit selects one of two different clocking protocols. refer to figure 7-2 and 7.4 clock phase and polarity controls . address: $0028 bit 7654321bit 0 read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu u = unaffected figure 7-3. spi control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi registers mc68hc711d3 ? rev. 2 data sheet motorola serial peripheral interface (spi) 93 spr1 and spr0 ? spi clock rate select bits these two serial peripheral rate bits select one of four baud rates to be used as sck if the device is a master; however, they have no effect in the slave mode. 7.7.2 spi status register spif ? spi transfer complete flag spif is set upon completion of data transfer between the processor and the external device. if spif goes high, and if sp ie is set, a serial peripheral interrupt is generated. to clear the spif bit, read the spsr with spif set, then access the spdr. unless spsr is read (with spif set) first, attempts to write spdr are inhibited. wcol ? write collision bit clearing the wcol bit is accomplished by reading the spsr (with wcol set) followed by an access of spdr. refer to 7.5.4 slave select (ss) and 7.6 spi system errors . 0 = no write collision 1 = write collision bit 5 ? not implemented always reads 0. modf ? mode fault bit to clear the modf bit, read the spsr (w ith modf set), then write to the spcr. refer to 7.5.4 slave select (ss) and 7.6 spi system errors . 0 = no mode fault 1 = mode fault bits 3?0 ? not implemented always reads 0 table 7-1. spi clock rates spr1 and spr0 e clock divide by frequency at e = 2 mhz (baud) 0 0 2 1.0 mhz 0 1 4 500 khz 1 0 16 125 khz 1 1 32 62.5 khz address: $0029 bit 7654321bit 0 read: spifwcol0modf0000 write: reset:00000000 figure 7-4. spi status register (spsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) data sheet mc68hc711d3 ? rev. 2 94 serial peripheral interface (spi) motorola 7.7.3 spi data i/o register the spi data i/o register (spdr) is used when transmitting or receiving data on the serial bus. only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. at the completion of transferring a byte of data, the spif status bit is set in both the master and slave devices. a read of the spdr is actually a read of a buffer. to prevent an overrun and the loss of the byte that caused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. note: spi is double buffered in and single buffered out. address: $002a bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 7-5. spi data i/o register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 95 data sheet ? mc68hc711d3 section 8. programmable timer 8.1 introduction the m68hc11 timing system is composed of five clock divider chains. the main clock divider chain includes a 16-bit fr ee-running counter, whic h is driven by a programmable prescaler. the main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. two prescaler control bits select the prescale rate. the prescaler output divides the system clock by 1, 4, 8, or 16. taps off of this main clocking chain drive circuitry that generat es the slower clocks used by the pulse accumulator, the real-time interrupt (rti ), and the computer operating properly (cop) watchdog subsystems. refer to figure 8-1 . all main timer system activities are re ferenced to this free-running counter. the counter begins incrementing from $0000 as the microcontroller unit (mcu) comes out of reset, and continues to the maximum count, $ffff. at the maximum count, the counter rolls over to $0000, sets an overflow flag, and continues to increment. as long as the mcu is running in a normal operating mode, there is no way to reset, change, or interrupt the counting. the c apture/compare subsystem features three input capture channels, four output compare channels, and one channel that can be selected to perform either input capture or output compare. each of the three input capture functions has its own 16-bit in put capture register (time capture latch) and each of the output compare functions has its own 16-bit compare register. all timer functions, including the timer overfl ow and rti have their own interrupt controls and separate interrupt vectors. the pulse accumulator contains an 8-bit counter and edge select logic. the pulse accumulator can operate in either event counting or gated time accumulation modes. during event counting mode, the pulse accumulator's 8-bit counter increments when a specified edge is detected on an input signal. during gated time accumulation mode, an internal clock sour ce increments the 8-bit counter while an input signal has a predetermined logic level. rti is a programmable periodic interrupt ci rcuit that permits pacing the execution of software routines by selecting one of four interrupt rates. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 96 programmable timer motorola figure 8-1. timer clock divider chains oscillator and clock generator as e clock spi sci receiver clock sci transmit clock e 2 6 pulse accumulator tcnt tof real-time interrupt e 2 13 4 e2 15 rq q s r q q s force cop reset system reset clear cop timer ff2 ff1 (divide by four) internal bus clock (ph2) ic/oc 16 cr1 and cr0 prescaler (1, 4, 16, 64) prescaler ( 2, 4, 16, 32) spr1 and spr0 prescaler ( 1, 3, 4, 13) scp1 and scp0 prescaler ( 1, 2, 4, 8) rtr1 and rtr0 prescaler ( 1, 2, 4,....128) scr2?scr0 prescaler ( 1, 4, 8, 16) pr1 and pr0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer structure mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 97 the cop watchdog clock input (e 2 15 ) is tapped off of the free-running counter chain. the cop automatically times out unless it is serviced within a specific time by a program reset sequence. if the cop is allowed to time out, a reset is generated, which drives the reset pin low to reset the mcu and the external system. refer to table 8-1 for crystal related frequencies and periods. 8.2 timer structure figure 8-2 shows the capture/compare system block diagram. the port a pin control block includes logic for timer func tions and for general-purpose input/output (i/o). for pins pa2, pa1, and pa0, this block contains both the edge-detection logic and the control logic that enables the selection of which edge triggers an input capture. the digital level on pa2?pa0 can be read at any time (read porta register), even if the pin is being used fo r the input capture function. pins pa6?pa4 are used for either general-purpose output or as output compare pins. pin pa3 can be used for general-purpose i/o, input capture 4, output compare 5, or output compare 1. when one of these pins is being used for an output compare function, it cannot be written directly as if it were a general-purpose output. each of the output compare functions (oc5?oc2) is related to one of the port a output pins. output compare 1 (oc1) has extra control logic, allowing it optional control of any combination of the pa7?pa3 pins. the pa7 pin can be used as a general-purpose i/o pin, as an input to the pulse accumulator, or as an oc1 output pin. table 8-1. timer summary control bits xtal frequencies 4.0 mhz 8.0 mhz 12.0 mhz other rates 1.0 mhz 2.0 mhz 3.0 mhz (e) 1000 ns 500 ns 333 ns (1/e) pr1 and pr0 main timer count rates 0 0 1 count ? overflow ? 1.0 s 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms (e/1) (e/2 16 ) 0 1 1 count ? overflow ? 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 87.381 ms (e/4) (e/2 18 ) 1 0 1 count ? overflow ? 8.0 s 524.29 ms 4.0 s 262.14 ms 2.667 s 174.76 ms (e/8) (e/2 19 ) 1 1 1 count ? overflow ? 16.0 s 1.049 s 8.0 s 524.29 ms 5.333 s 349.52 ms (e/16) (e/2 20 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 98 programmable timer motorola figure 8-2. capture/compare block diagram 8.3 input capture the input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. software ca n store latched values and use them to compute the periodicity and duration of event s. for example, by storing the times mcu e 16-bit latch clk 4 5 6 7 8 bit 7 bit 6 bit 5 bit 4 bit 3 oc1i oc2i oc3i oc4i i4/o5i tflg 1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f pa3/ic4/ pa4/oc4/ pa5/oc3/ pa6/oc2/ pa7/oc1/ i4/o5 16-bit comparator = toc1 (hi) toc1 (lo) 16-bit comparator = toc2 (hi) toc2 (lo) 16-bit comparator = toc3 (hi) toc3 (lo) 16-bit comparator = toc4 (hi) toc4 (lo) 16-bit comparator = ti4/o5 (hi) ti4/o5 (lo) 16-bit free running counter tcnt (hi) tcnt (lo) 9 toi tof prescaler ? divide by 1, 4, 8, 16 pr1 16-bit timer bus oc5 ic4 tmsk 1 interrupt enables cforc port a pins pa0/ic3 3 2 1 bit 2 bit 1 bit 0 ic1i ic2i ic3i ic1f ic2f ic3f pa1/ic2 pa2/ic1 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk pr0 clock pai oc1 oc1 oc1 oc5/oc1 port a pin control to pulse accumulator interrupt requests (further qualified by i bit in ccr) force output compare taps for rtl, cop watchdog, and pulse accumulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer input capture mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 99 of successive edges of an incoming signal, software can determine the period and pulse width of a signal. to measure peri od, two successive edges of the same polarity are captured. to measure pulse width, two alternate polarity edges are captured. in most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to the ph2 clock. these asynchronous capture requests are synchronized to ph2 so that the latching occurs on the opposite half cycle of ph2 from when the timer counter is being incremented. this synchronization process introduces a delay from when the edge occurs to when the counter value is detected. because these delays offset each other when the time between two edges is being measured, the delay can be ignored. when an input capture is being used with an output compare, there is a similar delay between the actual compare point and when the output pin changes state. the control and status bits that implement the input capture functions are contained in the pactl, tctl2, tmsk1, and tflg1 registers. to configure port a bit 3 as an input c apture, clear the ddra3 bit of the pactl register. note that this bit is cleared out of reset. to enable pa3 as the fourth input capture, set the i4/o5 bit in the pactl register. otherwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the ddra3 bit is set (configuring pa3 as an output), and ic4 is enabled, then writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/o5 register is acting as ic4. 8.3.1 timer control 2 register use the control bits of timer control 2 register (tctl2) to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture function. the input captur e functions operate independently of each other and can capture the same tcnt value if the input edges are detected within the same timer count cycle. edgxb and edgxa ? input capture edge control there are four pairs of these bits. each pair is cleared to 0 by reset and must be encoded to configure the corresponding input capture edge detector circuit. ic4 address: $0021 bit 7654321bit 0 read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset:00000000 figure 8-3. timer control 2 register (tctl2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 100 programmable timer motorola functions only if the i4/o5 bi t in pactl is set. refer to table 8-2 for timer control configuration. 8.3.2 timer input capture registers when an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel transfer. timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase two clock so that the count value is stable whenever a capture occurs. the timer input capture (ticx) registers are not affected by reset. input capture values ca n be read from a pair of 8-bit read-only registers. a read of the high-order byte of an input capture register pair inhibits a new capture transfer for one bus cycle. if a double-byte read instruction, such as ldd, is used to read the captured value, coherency is assured. when a new input capture occurs immediately after a high-orde r byte read, transfer is delayed for an additional cycle but the value is not lost. table 8-2. timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge address: $0010 ? tic1 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0011 ? tic1 (low) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset address: $0012 ? tic2 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset = unimplemented figure 8-4. timer input capture registers (ticx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer input capture mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 101 8.3.3 timer input capture 4/output compare 5 register use timer input capture 4/output compare 5 (ti4/o5) as either an input capture register or an output compare register, depending on the function chosen for the i4/o5 pin. to enable it as an input capture pin, set the i4/o5 bit in the pulse accumulator control register (pactl) to logic level 1. to use it as an output compare register, set the i4/o5 bit to a logic level 0. refer to 8.7 pulse accumulator . address: $0013 ? tic2 (low) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset address: $0014 ? tic3 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0015 ? tic3 (low) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented figure 8-4. timer input capture registers (ticx) (continued) address: $001e ? ti4/o5 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001f ? ti4/o5 (low) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 = unimplemented figure 8-5. timer input capture 4/output compare 5 register (ti4/o5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 102 programmable timer motorola 8.4 output compare (oc) use the output compare (oc) function to program an action to occur at a specific time ? when the 16-bit counter reaches a specified value. for each of the five output compare functions, there is a separate 16-bit compare register and a dedicated 16-bit comparator. the value in the compare register is compared to the value of the free-running counter on every bus cycle. when the compare register matches the counter value, an output compare status flag is set. the flag can be used to initiate the automatic actions for that output compare function. to produce a pulse of a specific duration, write to the output compare register a value representing the time the leading edge of the pulse is to occur. the output compare circuit is configured to set the appropriate output either high or low, depending on the polarity of the pulse being produced. after a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. a value representing the width of the pulse is added to the original value, and then is written to the output compare register. because the pin state changes occur at spec ific values of the free-running counter, the pulse width can be controlled accurately at the resolution of the free-running counter, independent of software latencies. to generate an output signal of a specific frequency and duty cycle, repeat this pulse-generating procedure. there are four 16-bit read/write output compare registers: toc1, toc2, toc3, and toc4, and the ti4/o5 register, which functions under software control as either ic4 or oc5. each of the oc registers is set to $ffff on reset. a value written to an oc register is compared to the free-running counter value during each e-clock cycle. if a match is found, the particular output compare flag is set in timer interrupt flag register 1 (tflg1). if that particular interrupt is enabled in the timer interrupt mask register 1 (tmsk1), an interrupt is generated. in addition to an interrupt, a specified action can be initiated at one or more timer output pins. for oc5?oc2, the pin action is controlled by pairs of bits (omx and olx) in the tctl1 register. the output action is taken on each successful compare, regardless of whether the ocxf flag in the tflg1 register was previously cleared. oc1 is different from the other output compares in that a successful oc1 compare can affect any or all five of the oc pins . the oc1 output action taken when a match is found is controlled by two 8-bit regi sters with three bits unimplemented: the output compare 1 mask register, oc1m , and the output compare 1 data register, oc1d. oc1m specifies which port a outputs are to be used, and oc1d specifies what data is placed on these port pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer output compare (oc) mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 103 8.4.1 timer output compare registers all output compare registers are 16-bit read-write. each is initialized to $ffff at reset. if an output compare register is not used for an output compare function, it can be used as a storage location. a write to the high-order byte of an output compare register pair inhibits the output compare function for one bus cycle. this inhibition prevents inappropriate subs equent comparisons. coherency requires a complete 16-bit read or write. however, if coherency is not needed, byte accesses can be used. for output compare functions, write a comparison value to output compare registers toc1?toc4 and ti4/o5. when tcnt value matches the comparison value, specified pin actions occur. address: $0016 ? toc1 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0017 ? toc1 (low) bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 address: $0018 ? toc2 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0019 ? toc2 (low) bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 address: $001a ? toc3 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 figure 8-6. timer output capture registers (tocx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 104 programmable timer motorola 8.4.2 timer compare force register the timer compare force register (c forc) allows forced early compares. foc1?foc5 correspond to the five output compares. these bits are set for each output compare that is to be forced. the action taken as a result of a forced compare is the same as if there were a match between the ocx register and the free-running counter, except that the corresponding interrupt status flag bits are not set. the forced channels trigger their prog rammed pin actions to occur at the next timer count transition after the write to cforc. the cforc bits should not be used on an output compare function that is programmed to toggle its output on a successful compare because a normal compare that occurs immediately before or after the force can result in an undesirable operation. foc1?foc5 ? write 1s to force compare bits 0 = not affected 1 = output x action occurs bits 2?0 ? not implemented, always read 0. address: $001b ? toc3 (low) bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 address: $001c ? toc4 (high) bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001d ? toc4 (low) bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 8-6. timer output capture registers (tocx) (continued) address: $000b bit 7654321bit 0 read: foc1 foc2 foc3 foc4 foc5 0 0 0 write: reset:00000000 figure 8-7. timer compare force register (cforc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer output compare (oc) mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 105 8.4.3 output compare 1 mask register use oc1m with oc1 to specify the bits of port a that are affected by a successful oc1 compare. the bits of the oc1m register correspond to pa7?pa3. oc1m7?oc1m3 ? output compare masks 0 = oc1 disabled 1 = oc1 enabled to control the corresponding pin of port a bits 2?0 ? not implemented; always read 0. set bit(s) to enable oc1 to control corresponding pin(s) of port a. 8.4.4 output compare 1 data register use this register with oc1 to specify the data that is to be stored on the affected pin of port a after a successful oc1 compare. when a successful oc1 compare occurs, a data bit in oc1d is stored in the corresponding bit of port a for each bit that is set in oc1m. if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits 2?0 ? not implemented; always read 0. address: $000c bit 7654321bit 0 read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 write: reset:00000000 figure 8-8. output compare 1 mask register (oc1m) address: $000d bit 7654321bit 0 read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 write: reset:00000000 figure 8-9. output compare 1 data register (oc1d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 106 programmable timer motorola 8.4.5 timer counter register the 16-bit read-only timer count register (tcnt) contains the prescaled value of the 16-bit timer. a full counter read addres ses the most significant byte (msb) first. a read of this address causes the least si gnificant byte (lsb) to be latched into a buffer for the next cpu cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the msb read cycle. in normal modes, tcnt is read-only. 8.4.6 timer control 1 register the bits of the timer control 1 register (tctl1) specify the action taken as a result of a successful ocx compare. om2?om5 ? output mode bits ol2?ol5 ? output level bits these control bit pairs are encoded to specify the action taken after a successful ocx compare. oc5 functions only if the i4 /o5 bit in the pactl register is clear. refer to table 8-3 for the coding. address: $000e ? tcnt high bit 15 14 13 12 11 10 9 bit 8 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 08 write: reset:00000000 address: $000f ? tcnt low bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 8-10. timer counter registers (tcnt) address: $0020 bit 7654321bit 0 read: om2ol2om3ol3om4ol4om5ol5 write: reset:00000000 figure 8-11. timer control 1 register (tctl1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer output compare (oc) mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 107 8.4.7 timer interrupt mask 1 register the timer interrupt mask 1 register (tmsk1) is an 8-bit register used to enable or inhibit the timer input capture and output compare interrupts. oc1i?oc4i ? output compare x interrupt enable bits if the ocxi enable bit is set when the ocxf flag bit is set, a hardware interrupt sequence is requested. i4/o5i ? input capture 4 or output compare 5 interrupt enable bit when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt enable bit. when i4/o5 in pactl is 0, i4/o5i is the output compare 5 interrupt enable bit. ic1i?ic3i ? input capture x interrupt enable bits if the icxi enable bit is set when the icxf flag bit is set, a hardware interrupt sequence is requested. note: bits in tmsk1 correspond bit for bit with fl ag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. table 8-3. timer output compare actions omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1 address: $0022 bit 7654321bit 0 read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset:00000000 figure 8-12. timer interrupt mask 1 register (tmsk1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 108 programmable timer motorola 8.4.8 timer interrupt flag 1 register the timer interrupt flag 1 register (tflg1) bits indicate when timer system events have occurred. coupled with the bits of tmsk1, the bits of tflg1 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg1 corresponds to a bit in tmsk1 in the same position. clear flags by writing a 1 to the corresponding bit position(s). oc1f?oc5f ? output compare x flag set each time the counter matches output compare x value i4/o5f ? input capture 4/output compare 5 flag set by ic4 or oc5, depending on the function enabled by i4/o5 bit in pactl ic1f?ic3f ? input capture x flag set each time a selected active edge is detected on the icx input line 8.4.9 timer interrupt mask 2 register the timer interrupt mask 1 register (tmsk2) is an 8-bit register used to enable or inhibit timer overflow and real-time interrupt s. the timer prescaler control bits are included in this register. toi ? timer overflow interrupt enable bit 0 = tof interrupts disabled 1 = interrupt requested when tof is set to 1 rtii ? real-time interrupt enable bit refer to 8.5 real-time interrupt . paovi ? pulse accumulator overflow interrupt enable bit refer to 8.7 pulse accumulator . address: $0023 bit 7654321bit 0 read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset:00000000 figure 8-13. timer interrupt flag 1 register (tflg1) address: $0024 bit 7654321bit 0 read: toi rtii paovi paii 0 0 pr1 pr0 write: reset:00000000 figure 8-14. timer interrupt mask 2 register (tmsk2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer output compare (oc) mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 109 paii ? pulse accumulator input edge interrupt enable bit refer to 8.7 pulse accumulator . note: bits in tmsk2 correspond bit for bit with fl ag bits in tflg2. ones in tmsk2 enable the corresponding interrupt sources. pr1 and pr0 ? timer prescaler select bits these bits are used to select the pres caler divide-by ratio. in normal modes, pr1 and pr0 can be written once only, and t he write must be within 64 cycles after reset. refer to table 8-4 for specific timing values. 8.4.10 timer interrupt flag 2 register the timer interrupt flag 2 register (tflg2) bits indicate when certain timer system events have occurred. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif ? real-time (periodic) interrupt flag refer to 8.5 real-time interrupt . paovf ? pulse accumulator overflow interrupt flag refer to 8.7 pulse accumulator . paif ? pulse accumulator input edge interrupt flag refer to 8.7 pulse accumulator . bits 3?0 ? not implemented always read 0. table 8-4. timer prescale pr1 and pr0 prescaler 0 0 1 0 1 4 1 0 8 1 1 16 address: $0025 bit 7654321bit 0 read: tofrtifpaovfpaif0000 write: reset:00000000 figure 8-15. timer interrupt flag 2 register (tflg2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 110 programmable timer motorola 8.5 real-time interrupt the real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configur ed by two bits (rtr1 and rtr0) in the pulse accumulator control (pactl) register. the rtii bit in the tmsk2 register enables the interrupt capability. the four different rates available are a product of the mcu oscillator frequency and the value of bits rtr1 and rtr0. refer to table 8-5 for the periodic real-time interrupt rates. the clock source for the rti function is a free-running clock that cannot be stopped or interrupted except by reset. this cloc k causes the time between successive rti timeouts to be a constant that is independent of the software latencies associated with flag clearing and service. for this reason, an rti period starts from the previous timeout, not from when rtif is cleared. every timeout causes the rtif bit in tflg2 to be set, and if rtii is set, an interrupt request is generated. after reset, one entire real-time interrupt period elapses before the rtif flag is set for the first time. refer to the tmsk2, tflg2, and pactl registers. 8.5.1 timer interrupt mask 2 register the timer interrupt mask 2 register (tmsk2) contains the real-time interrupt enable bits. toi ? timer overflow interrupt enable bit refer to 8.4 output compare (oc) . table 8-5. periodic real-time interrupt rates rtr1 and rtr0 e = 1 mhz e = 2 mhz e = 3 mhz e = x mhz 0 0 0 1 1 0 1 1 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms (e/2 13 ) (e/2 14 ) (e/2 15 ) (e/2 16 ) address: $0024 bit 7654321bit 0 read: toi rtii paovi paii 0 0 pr1 pr0 write: reset:00000000 figure 8-16. timer interrupt mask 2 register (tmsk2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer real-time interrupt mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 111 rtii ? real-time interrupt enable bit 0 = rtif interrupts disabled 1 = interrupt requested paovi ? pulse accumulator overflow interrupt enable bit refer to 8.7 pulse accumulator . paii ? pulse accumulator input edge bit refer to 8.7 pulse accumulator . bits 3?2 ? unimplemented always read 0. pr1 and pr0 ? timer prescaler select bits refer to table 8-4 . note: bits in tmsk2 correspond bit for bit with fl ag bits in tflg2. ones in tmsk2 enable the corresponding interrupt sources. 8.5.2 timer interrupt flag 2 register bits of the timer interrupt flag 2 register (tflg2) indicate the occurrence of timer system events. coupled with the four high-o rder bits of tmsk2, the bits of tflg2 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif ? real-time interrupt flag the rtif status bit is automatically set to 1 at the end of every rti period. to clear rtif, write a byte to tflg2 with bit 6 set. paovf ? pulse accumulator overflow interrupt flag refer to 8.7 pulse accumulator . paif ? pulse accumulator input edge interrupt flag refer to 8.7 pulse accumulator . bits 3?0 ? not implemented always read 0. address: $0025 bit 7654321bit 0 read: tofrtifpaovfpaif0000 write: reset:00000000 figure 8-17. timer interrupt flag 2 register (tflg2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 112 programmable timer motorola 8.5.3 pulse accumulator control register bits rtr1 and rtr0 of the pulse accumulator control register (pactl) select the rate for the real-time interrupt system. bit ddra3 determines whether port a bit three is an input or an output when used for general-purpose i/o. the remaining bits control the pulse accumulator. ddra7 ? data direction control for port a bit 7 refer to 8.7 pulse accumulator . paen ? pulse accumulator system enable bit refer to 8.7 pulse accumulator . pamod ? pulse accumulator mode bit refer to 8.7 pulse accumulator . pedge ? pulse accumulator edge control bit refer to 8.7 pulse accumulator . ddra3 ? data direction register for port a bit 3 refer to section 5. input/output (i/o) ports . i4/o5 ? input capture 4/output compare 5 bit refer to 8.3 input capture . rtr1 and rtr0 ? rti interrupt rate select bits these two bits determine the rate at wh ich the rti system requests interrupts. the rti system is driven by an e divided by 2 13 rate clock that is compensated so it is independent of the timer prescaler. these two control bits select an additional division factor. see table 8-6 . address: $0026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 8-18. pulse accumulator control register (pactl) table 8-6. real-time interrupt rates rtr1 and rtr0 e = 1 mhz e = 2 mhz e = 3 mhz e = x mhz 0 0 0 1 1 0 1 1 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms (e/2 13 ) (e/2 14 ) (e/2 15 ) (e/2 16 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer computer operating properly watchdog function mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 113 8.6 computer operating properly watchdog function the clocking chain for the cop function, tapped off of the main timer divider chain, is only superficially related to the main timer system. the cr1 and cr0 bits in the option register and the nocop bit in t he config register determine the status of the cop function. refer to section 4. resets, interrupts, and low-power modes for a more detailed discussion of the cop function. 8.7 pulse accumulator the mc68hc711d3 has an 8-bit counter that can be configured to operate either as a simple event counter or for gated time accumulation, depending on the state of the pamod bit in the pactl register. refer to the pulse accumulator block diagram, figure 8-19 . figure 8-19. pulse accumulator pacnt 8-bit counter 2:1 mux pa7/ enable overflow 1 2 interrupt requests internal data bus input buffer and edge detection pactl control tflg2 interrupt status tmsk2 int enables paovi paii ddra7 paen pamod pedge paovf paif output buffer pai edge paen e 64 clock (from main timer) pai/oc1 from main timer oc1 disable flag setting f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 114 programmable timer motorola in the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. the maximum clocking rate for the external event counting mode is the e clock divided by two. in gated time accumulation mode, a free-running e-clock 64 signal drives the 8-bit counter, but only while the external pai pin is activated. refer to table 8-7 . the pulse accumulator counter can be read or written at any time. pulse accumulator control bits are also located within two timer registers, tmsk2 and tflg2, as described here. 8.7.1 pulse accumulator control register four of the pulse accumulator control register (pactl) bits control an 8-bit pulse accumulator system. another bit enables either the oc5 function or the ic4 function, while two other bits select the rate for the real-time interrupt system. ddra7 ? data direction control for port a bit 7 the pulse accumulator uses port a bit 7 as the pai input, but the pin can also be used as general-purpose i/o or as an output compare. note: even when port a bit 7 is configured as an output, the pin still drives the input to the pulse accumulator. refer to section 5. input/output (i/o) ports for more information. paen ? pulse accumulator system enable bit 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ? pulse accumulator mode bit 0 = event counter 1 = gated time accumulation table 8-7. pulse accumulator timing in gated mode selected crystal common xtal frequencies 4.0 mhz 8.0 mhz 12.0 mhz cpu clock (e) 1.0 mhz 2.0 mhz 3.0 mhz cycle time (1/e) 1000 ns 500 ns 333 ns (e/2 6 ) (e/2 14 ) 1 count - overflow - 64.0 s 16.384 ms 32.0 s 8.192 ms 21.33 s 5.461 ms address: $0026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 8-20. pulse accumulator control register (pactl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer pulse accumulator mc68hc711d3 ? rev. 2 data sheet motorola programmable timer 115 pedge ? pulse accumulator edge control bit this bit has different meanings depending on the state of the pamod bit, as shown in table 8-8 . ddra3 ? data direction register for port a bit 3 refer to section 5. input/output (i/o) ports . i4/o5 ? input capture 4/output compare 5 bit refer to 8.3 input capture . rtr1 and rtr0 ? rti interrupt rate select bits refer to 8.5 real-time interrupt . 8.7.2 pulse accumulator count register the 8-bit read/write pulse accumulator count register (pacnt) contains the count of external input events at the pai input or the accumulated count. the counter is not affected by reset and can be read or written at any time. counting is synchronized to the internal ph2 clock so that incrementing and reading occur during opposite half cycles. 8.7.3 pulse accumulator status and interrupt bits the pulse accumulator control bits, paovi and paii, paovf, and paif are located within timer registers tmsk2 and tflg2. paovi and paovf ? pulse accumulator interrupt enable and overflow flag the paovf status bit is set each time the pulse accumulator count rolls over from $ff to $00. to clear this status bit, write a 1 in the corresponding data bit position (bit 5) of the tflg2 register. the paovi control bit allows configuring the pulse accumulator overflow for polle d or interrupt-driven operation and does table 8-8. pulse accumulator edge control pamod pedge action on clock 0 0 pai falling edge increments the counter. 0 1 pai rising edge increments the counter. 1 0 a 0 on pai inhibits counting. 1 1 a 1 on pai inhibits counting. address: $0027 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 8-21. pulse accumulator count register (pacnt) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer data sheet mc68hc711d3 ? rev. 2 116 programmable timer motorola not affect the state of paovf. when paovi is 0, pulse accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which requires paovf to be polled by user software to determine when an overflow has occurred. when the paovi control bi t is set, a hardware interrupt request is generated each time paovf is set. before leaving the interrupt service routine, software must clear paovf by writing to the tflg2 register. paii and paif ? pulse accumulator input edge interrupt enable and flag the paif status bit is automatically set each time a selected edge is detected at the pa7/pai/oc1 pin. to clear this status bit, write to the tflg2 register with a 1 in the corresponding data bit position (bit 4). the paii control bit allows configuring the pulse accumulator input edge detect for polled or interrupt-driven operation but does not affect setting or clearing the paif bit. when paii is 0, pulse accumulator input interrupts are inhibited, and the system operates in a polled mode. in this mode, the paif bit must be polled by user software to determine when an edge has occurred. when the paii control bit is set, a hardware interrupt request is generated each time paif is set. before leaving the interrupt service routine, so ftware must clear paif by writing to the tflg register. address: $0024 bit 7654321bit 0 read: toi rtii paovi paii 0 0 pr1 pr0 write: reset:00000000 figure 8-22. timer interrupt mask 2 register (tmsk2) address: $0025 bit 7654321bit 0 read: tofrtifpaovfpaif0000 write: reset:00000000 figure 8-23. timer interrupt flag 2 register (tflg2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 117 data sheet ? mc68hc711d3 section 9. electrical characteristics 9.1 introduction this section contains el ectrical specifications. 9.2 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 9.5 dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any volta ge higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating symbol value unit supply voltage v dd ?0.3 to +7.0 v input voltage v in ?0.3 to +7.0 v current drain per pin (1) excluding v dd , v ss, v rh, and v rl 1. one pin at a time, observing maximum power dissipation limits i d 25 ma storage temperature t stg ?55 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 118 electrical characteristics motorola 9.3 functional operat ing temperature range 9.4 thermal characteristics rating symbol value unit operating temperature range mc68hc711d3 mc68hc711d3v t a t l to t h ?40 to +85 ?40 to +105 c characteristic symbol value unit average junction temperature t j t a + (p d ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 40-pin plastic dual in-line package (dip) 44-pin plastic leaded chip carrier (plcc) 44-pin plastic quad flat pack (qfp) ja 50 50 85 c/w total power dissipation (1) p d p int + p i/o k / t j + 273 c w device internal power dissipation p int i dd v dd w i/o pin power dissipation (2) p i/o user-determined w a constant (3) k p d (t a + 273 c) + ja p d 2 w/ c 1. this is an approximate value, neglecting p i/o . 2. for most applications, p i/o p int and can be neglected. 3. k is a constant pertaining to th e device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j , iteratively, for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics dc electrical characteristics mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 119 9.5 dc electrical characteristics characteristic (1) symbol min max unit output voltage (2) all outputs i load = 10.0 aall outputs except reset and moda v ol v oh ? v dd ? 0.1 0.1 ? v output high voltage (1) all outputs except i load = ? 0.8 ma, v dd = 4.5 v reset , extal, and moda v oh v dd ? 0.8 ? v output low voltage all outputs except xtal i load = 1.6 ma v ol ? 0.4 v input high voltage all inputs except reset reset v ih 0.7 x v dd 0.8 x v dd v dd + 0.3 v dd + 0.3 v input low voltage all inputs v il v ss ? 0.3 0.2 x v dd v i/o ports, three-state leakage pa7, pa3, pc7?pc0, pd7?pd0, v in = v ih or v il moda/lir , reset i oz ? 10 a input leakage current v in = v dd or v ss irq , xirq v in = v dd or v ss modb/v stby i in ? ? 1 10 a ram standby voltagepower down v sb 4.0 v dd v ram standby currentpower down i sb ? 20 a total supply current (3) run: single-chip mode dc ? 2 mhz dc ? 3 mhz expanded multiplexed mode dc ? 2 mhz dc ? 3 mhz wait ? all peripheral functions shut down: single-chip mode dc ? 2 mhz dc ? 3 mhz expanded multiplexed mode dc ? 2 mhz dc ? 3 mhz stop ? no clocks, single-chip mode: dc ? 2 mhz dc ? 3 mhz i dd w idd s idd ? ? ? ? ? ? ? ? ? ? 15 27 27 35 6 15 10 20 100 150 ma ma a the dc electrical table continues on next page. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 120 electrical characteristics motorola figure 9-1. equivalent test load input capacitancepa3?pa0, irq , xirq , extal pa7, pc7?pc0, pd7?pd0, moda/lir , reset c in ? ? 8 12 pf power dissipation single-chip mode dc ? 2 mhz dc ? 3 mhz expanded multiplexed mode dc ? 2 mhz dc ? 3 mhz p d ? ? ? ? 85 150 150 195 mw eprom programming voltage v pp 11.75 12.75 v eprom programming time t pp 24ms 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. v oh specification for reset and moda is not applicable bec ause they are open-drain pins. v oh specification is not applicable to ports c and d in wired-or mode. 3. all ports configured as inputs: v il 0.2 v, v ih v dd ?0.2 v; no dc loads; extal is driven with a square wave; t cyc = 476.5 ns. characteristic (1) symbol min max unit pins r1 r2 c1 pa3?pa7 pb0?pb7 pc0?pc7 pd0, pd5?pd7 e 3.26 k 2.38 k 90 pf pd1?pd4 3.26 k 2.38 k 200 pf v dd c1 r2 r1 test point 1. full test loads are applied during all ac electrical timing measurements. equivalent test load (1) note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics dc electrical characteristics mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 121 figure 9-2. test methods clocks, strobes inputs 0.4 v nominal timing nom 20% of v dd 70% of v dd 0.4 v v ss ~ nom outputs 0.4 v dc testing clocks, strobes inputs spec timing 0.4 v spec outputs ac testing (note 1) spec ~ v dd ~ v ss ~ v dd ~ v dd ~ v dd ~ v ss v dd ? 0.8 v v dd ? 0.8 v 20% of v dd ~ v ss 20% of v dd 70% of v dd v dd ? 0.8 v 20% of v dd 70% of v dd 70% of v dd 20% of v dd note: 1. during ac timing measurement s, inputs are driven to 0.4 volts and v dd ? 0.8 volts while timing measurements are taken at the 20% and 70% of v dd points. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 122 electrical characteristics motorola 9.6 control timing figure 9-3. timer inputs characteristic (1) symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation f o dc 1.0 dc 2.0 dc 3.0 mhz e-clock period t cyc 1000 ? 500 ? 333 ? ns crystal frequency f xtal ?4.0?8.0?12.0mhz external oscillator frequency 4 f o dc 4.0 dc 8.0 dc 12.0 mhz processor contro l setup timet pcsu = 1/4 t cyc + 50 ns t pcsu 300 ? 175 ? 133 ? ns reset input pulse width (2) to guarantee external reset vector minimum input time can be preempted by internal reset pw rstl 8 1 ? ? 8 1 ? ? 8 1 ? ? t cyc mode programming setup time t mps 2?2?2? t cyc mode programming hold time t mph 10 ? 10 ? 10 ? ns interrupt pulse width, pw irq = t cyc + 20 ns irq edge-sensitive mode pw irq 1020 ? 520 ? 353 ? ns wait recovery startup time t wrs ? 4?4?4 t cyc timer pulse width pw tim = t cyc + 20 ns input capture pulse accumulator input pw tim 1020 ? 520 ? 353 ? ns 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. reset is recognized during the first clock cycle it is held lo w. internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles late r to determine the source of the interrupt. refer to section 5. input/output (i/o) ports for further details. notes: 1. rising edge sensitive input 2. falling edge sensitive input 3. maximum pulse accumulator clocki ng rate is e-clock frequency divided by 2. pa7 (2) (3) pa7 (1) (3) pa0?pa3 (2) pa0?pa3 (1) pw tim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 123 electrical characteristics control timing figure 9-4. por and external reset timing diagram t pcsu address moda, modb e extal v dd reset 4064 t cyc fffe fffe fffe new pc fffe ffff fffe fffe fffe new pc fffe ffff fffe t mph pw rstl t mps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc711d3 ? rev. 2 124 electrical characteristics motorola electrical characteristics figure 9-5. stop recovery timing diagram pw irq t stopdelay (3) irq (1) irq (2) or xirq e sp ? 8 sp ? 8 fff2 (fff4) new pc stop addr stop addr + 1 address (4) stop addr stop addr + 1 stop addr + 1 stop addr + 1 stop addr + 2 sp?sp?7 fff3 (fff5) opcode resume program with instruction which follows the stop instruction. notes: address (5) reset 1. edge sensitive irq pin (irqe bit = 1) 2. edge sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4064 t cyc if dly bit = 1 or 4 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0) as f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 125 electrical characteristics control timing figure 9-6. wait recovery timing diagram t pcsu pcl pch, yl, yh, xl, xh, a, b, ccr stack registers e r/w address wait addr wait addr + 1 irq , xirq , or internal interrupts note: reset also causes recovery from wait. sp sp ? 1 sp ? 2?sp ? 8 sp ? 8 sp ? 8?sp ? 8 sp ? 8 sp ? 8 sp ? 8 vector addr + 1 new pc t wrs vector addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc711d3 ? rev. 2 126 electrical characteristics motorola electrical characteristics figure 9-7. interrupt timing diagram e pw irq irq (1) irq (2) , xirq t pcsu or internal interrupt address sp sp ? 3 sp ? 6 sp ? 8 sp ? 8 new pc next opcode next op + 1 vector addr + 1 vector addr sp ? 7 sp ? 4 sp ? 5 sp ? 1 sp ? 2 op code ? ? pcl pch iyl iyh ixl ixh b a ccr ? ? vect msb vect lsb op code as address r/w notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics peripheral port timing mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 127 9.7 peripheral port timing figure 9-8. port write timing diagram figure 9-9. port read timing diagram characteristic (1) symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation (e-clock frequency) f o 1.0 1.0 2.0 2.0 3.0 3.0 mhz e-clock period t cyc 1000 ? 500 ? 333 ? ns peripheral data setup time (2) mcu read of ports a, b, c, and d t pdsu 100 ? 100 ? 100 ? ns peripheral data hold time (2) mcu read of ports a, b, c, and d t pdh 50 ? 50 ? 50 ? ns delay time, peripheral data write mcu write to port a mcu writes to ports b, c, and d t pwd = 1/4 t cyc + 150 ns t pwd ? ? 200 350 ? ? 200 225 ? ? 200 183 ns 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. port c and d timing is valid for active drive (cwom and dwom bits not set in pioc and spcr registers respectively). t pwd e mcu write to port previous port data previous port data new data valid new data valid ports b, c, d port a t pwd t pdh e mcu read of port t pdsu ports a, b, c, d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 128 electrical characteristics motorola 9.8 expansion bus timing num characteristic (1) symbol 1.0 mhz 2.0 mhz 3.0 mhz unit min max min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 dc 3.0 mhz 1 cycle time t cyc 1000 ? 500 ? 333 ? ns 2 pulse width, e low, pw el = 1/2 t cyc ? 23 ns pw el 477 ? 227 ? 146 ? ns 3 pulse width, e high, pw eh = 1/2 t cyc ? 28 ns pw eh 472 ? 222 ? 141 ? ns 4a e and as rise time t r ?20?20?20ns 4b e and as fall time t f ?20?20?15ns 9 address hold time (2)a , t ah = 1/8 t cyc ? 29.5 ns t ah 95.5 ? 33 ? 26 ? ns 12 non-muxed address valid time to e rise t av = pw el ? (t asd + 80 ns) (2)a t av 281.5 ? 94 ? 54 ? ns 17 read data setup time t dsr 30 ? 30 ? 30 ? ns 18 read data hold time (max = t mad )t dhr 0 145.5 0 83 0 51 ns 19 write data delay time, t ddw = 1/8 t cyc + 65.5 ns (2)a t ddw ? 190.5 ? 128 ? 71 ns 21 write data hold time, t dhw = 1/8 t cyc ? 29.5 ns (2)a t dhw 95.5 ? 33 ? 26 ? ns 22 muxed address valid time to e rise t avm = pw el ? (t asd + 90 ns) (2)a t avm 271.5 ? 84 ? 54 ? ns 24 muxed address valid time to as fall t asl = pw ash ? 70 ns t asl 151 ? 26 ? 13 ? ns 25 muxed address hold time, t ahl = 1/8 t cyc ? 29.5 ns (2)b t ahl 95.5 ? 33 ? 31 ? ns 26 delay time, e to as rise, t asd = 1/8 t cyc ? 9.5 ns (2)a t asd 115.5 ? 53 ? 31 ? ns 27 pulse width, as high, pw ash = 1/4 t cyc ? 29 ns pw ash 221 ? 96 ? 63 ? ns 28 delay time, as to e rise, t ased = 1/8 t cyc ? 9.5 ns (2)b t ased 115.5 ? 53 ? 31 ? ns 29 mpu address access time (2)a t acca = t cyc ? (pw el ? t avm ) ? t dsr ? t f t acca 744.5 ? 307 ? 196 ? ns 35 mpu access time , t acce = pw eh ? t dsr t acce ? 442 ? 192 ? 111 ns 36 muxed address delay (previous cycle mpu read) t mad = t asd + 30 ns (2)a(3) t mad 145.5 ? 83 ? 51 ? ns 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. input clocks with duty cycles other than 50% affect bus performa nce. timing parameters affect ed by input clock duty cycle are identified by (a) and (b). to recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 t cyc in the above formulas, where applicable: (a) (1-dc) 1/4 t cyc (b) dc 1/4 t cyc where: dc is the decimal va lue of duty cycle perc entage (high time). 3. formula only for dc to 2 mhz. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics expansion bus timing mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 129 figure 9-10. multiplexed expansion bus timing diagram e as 1 4 9 address/data (multiplexed) read write 12 2 3 4 4 4 29 35 17 18 19 21 25 24 27 36 22 26 28 address address data data r/w , address (non-mux) note: measurement points shown are 20% and 70% of v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 130 electrical characteristics motorola 9.9 serial peripher al interface timing num characteristic (1) symbol 2.0 mhz 3.0 mhz unit min max min max operating frequency master slave f op(m) f op(s) dc dc 0.5 2.0 dc dc 0.5 3.0 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 500 ? ? 2.0 333 ? ? t cyc ns 2 enable lead time master (2) slave t lead(m) t lead(s) ? 250 ? ? ? 240 ? ? ns 3 enable lag time master (2) slave t lag(m) t lag(s) ? 250 ? ? ? 240 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? 227 127 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? 227 127 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? 100 100 ? ? ns 8 access time (time to data acti ve from high-impedance state) slave t a 0 120 0 120 ns 9 disable time (hold time to high-impedance state) slave t dis ? 240 ? 167 ns 10 data valid (after enable edge) (3) t v(s) ? 240 ? 167 ns 11 data hold time (outputs) (after enable edge) t ho 0?0?ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 100 2.0 ? ? 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 100 2.0 ? ? 100 2.0 ns s 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. signal production depends on software. 3. assumes 200 pf load on all spi pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics serial peripheral interface timing mc68hc711d3 ? rev. 2 data sheet motorola electrical characteristics 131 figure 9-11. spi master timing (cpha = 0) figure 9-12. spi master timing (cpha = 1) see note note: this first clock edge is generated inte rnally but is not seen at the sck pin. sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) ss (input) 1 see note 11 msb in bit 6 - - - -1 lsb in master msb out master lsb out bit 6 - - - -1 10 12 13 ss is held high on master 5 4 13 12 11 (ref) 10 (ref) 13 4 5 12 note: this last clock edge is generated internally but is not seen at the sck pin. 4 5 5 4 1 see note 11 6 7 msb in lsb in master msb out master lsb out bit 6 - - - -1 10 13 12 12 13 sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) ss (input) ss is held high on master see note 12 13 bit 6 - - - -1 11 (ref) 10 (ref) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical characteristics data sheet mc68hc711d3 ? rev. 2 132 electrical characteristics motorola figure 9-13. spi slave timing (cpha = 0) figure 9-14. spi slave timing (cpha = 1) note: not defined but normally msb of character just received 4 2 5 5 4 1 8 see note msb out slave slave lsb out 6 7 msb in 10 bit 6 - - - -1 lsb in 11 12 13 3 9 sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) ss (input) 11 12 13 bit 6 - - - -1 note: not defined but normally lsb of character previ ously transmitted 4 2 10 6 7 5 5 4 1 8 msb in see note msb out 10 slave bit 6 - - - -1 lsb in slave lsb out 11 13 12 12 13 3 9 sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) ss (input) bit 6 - - - -1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola ordering information and mechanical specifications 133 data sheet ? mc68hc711d3 section 10. ordering informatio n and mechanical specifications 10.1 introduction this section provides ordering inform ation for the mc68hc711d3. in addition, mechanical specifications are provided for the following packaging options: 40-pin plastic dual in-line package (dip) 44-pin plastic leaded chip carrier (plcc) 44-pin plastic quad flat pack (qfp) 10.2 ordering information table 10-1. mc order numbers package type temperature mc order number 2 mhz 3 mhz 40-pin dip ?40 to +85c mc68hc711d3cp2 mc68hc711d3cp3 44-pin plcc ?40 to +85c mc68hc711d3cfn2 mc68hc711d3cfn3 ?40 to +105c mc68hc711d3vfn2 mc68hc711d3vfn3 44-pin qfp ?40 to +85c mc68hc711d3cfb2 mc68hc711d3cfb3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications data sheet mc68hc711d3 ? rev. 2 134 ordering information and mechanical specifications motorola 10.3 40-pin dip (case 711-03) notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 120 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications 44-pin plcc (case 777-02) mc68hc711d3 ? rev. 2 data sheet motorola ordering information and mechanical specifications 135 10.4 44-pin plcc (case 777-02) -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 1.02 s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t 2 10 notes: 1. datums -l-, -m-, and -n- are determined where top of lead sholders exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimension r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. diminsion h does not include dambar protrusion or intrusion. the dambar protusion(s) shall not cause the h diminsion to be greater than 0.037 (0.940136). the dambar intrusion(s) shall not cause the h diminision to smaller than 0.025 (0.635). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications data sheet mc68hc711d3 ? rev. 2 136 ordering information and mechanical specifications motorola 10.5 44-pin qfp (case 824a-01) notes: 1. 1. dimensioning and to lerancing per ansi y14.5m, 1982. 2. 2. controlling dimension: millimeter. 3. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. 5. dimensions s and v to be determined at seating plane -c-. 6. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. l 33 34 23 22 44 111 12 detail a -d- -a- a s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b s b s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b v l -b- -c- seating plane m m e h g c -h- datum plane detail c 0.01 (0.004) m -h- datum plane t r k q w x detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.10 0.079 0.083 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h --- 0.25 --- 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 8.00 ref 0.315 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 --- 0.005 --- u 0 --- 0 --- v 12.95 13.45 0.510 0.530 w 0.40 --- 0.016 --- x 1.6 ref 0.063 ref detail a b b -a-, -b-, -d- s a-b m 0.20 (0.008) d s c f n section b-b j d base metal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola mc68hc11d3 and mc68hc11d0 137 data sheet ? mc68hc711d3 appendix a. mc68hc11d3 and mc68hc11d0 a.1 introduction the mc68hc11d3 and mc68hc11d0 ar e read-only memory (rom) based high-performance microcontrollers (mcu) based on the mc68hc11e9 design. members of the dx series are derived from the same mask and feature a high-speed multiplexed bus capable of runni ng at up to 3 mhz and a fully static design that allows operations at frequencies to dc. the only difference between the mcus in the dx series is whether the rom has been tested and guaranteed. the information contained in this document applies to both the mc68hc11d3 and mc68hc11d0 with the differences given in this appendix. features of the mc68hc11d3 and mc68hc11d0 include: 4 kbytes of on-chip rom (mc68hc11d3) 0 bytes of on-chip rom (mc68hc11d0) 192 bytes of on-chip random-access memory (ram) all saved during standby 16-bit timer system: ? three input capture (ic) channels ? four output compare (oc) channels ? one ic or oc software-selectable channel 32 input/output (i/o) pins: ? 26 bidirectional i/o pins ? 3 input-only pins ? 3 output-only pins available in these packages: ? 44-pin plastic leaded chip carrier (plcc) ? 44-pin quad flat pack (qfp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11d3 and mc68hc11d0 data sheet mc68hc711d3 ? rev. 2 138 mc68hc11d3 and mc68hc11d0 motorola a.2 block diagram figure a-1. mc68hc11d3 block diagram port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 mode control interrupt control moda/lir modb/v stby reset irq xirq xtal extal e clock logic oscillator pai/oc1 oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5/oc1 ic1 ic2 ic3 timer pulse accumulator cop periodic interrupt mc68hc11d3 ? 4 kbytes rom pd7/r/w pd6/as pd5 pd4 pd3 pd2 pd1 pd0 data direction register d port d data direction register c port c data direction register b port b a15 a14 a13 a12 a11 a10 a9 a8 a7/d7 a6/d6 a5/d5 a4/d4 a3/d3 a2/d2 a1/d1 a0/d0 multiplexed address/data bus 192 bytes ram serial peripheral interface (spi) serial communications interface (sci) mc68hc11d3 cpu core ss sck mosi miso txd rxd v ss v dd ev ss mc68hc11d0 ? 0 bytes rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11d3 and mc68hc11d0 mc68hc711d3 ? rev. 2 data sheet motorola mc68hc11d3 and mc68hc11d0 139 a.3 pin assignments figure a-2. pin assignments for 44-pin plcc figure a-3. pin assignments for 44-pin qfp pc4/a4/d4 pc5/a5/d5 pc6/a6/d6 pc7/a7/d7 xirq pd7/r/w pd6/as reset irq pd0/rxd pd1/txd pb2/a10 pb3/a11 pb4/a12 pb5/a13 pb6/a14 pb7 nc pa0/ic3 pa1/ic2 pc3 pc2 pc1 pc0 v ss ev ss xtal extal e moda/lir modb/v stby pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai pa6/oc2 pa5/oc3 pa4/oc4 pa3/ic4/oc5/oc1 pa2/ic1 7 8 9 10 11 12 13 14 15 16 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 17 pb1/a9 38 pb0/a8 39 pc4 pc5 pc6 pc7 xirq pd7 pd6 reset irq pd0 pd1 pb2 pb3 pb4 pb5 pb6 pb7 nc pa0 pa1 pc3 pc2 pc1 pc0 ev ss v ss xtal extal e moda modb pd2 pd3 pd4 pd5 v dd pa7 pa6 pa5 pa4 pa3 pa2 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 43 42 41 40 39 38 37 36 35 34 pb1 32 pb0 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11d3 and mc68hc11d0 data sheet mc68hc711d3 ? rev. 2 140 mc68hc11d3 and mc68hc11d0 motorola a.4 memory map figure a-4. mc68hc11dx (1) memory map a.5 mc68hc11d3 and mc68hc11d 0 electrical characteristics the parameters given in section 9. electrical characteristics apply to the mc68hc11d3 and mc68hc11d0 with the exceptions given here. a.5.1 functional operat ing temperature range a.5.2 thermal characteristics 1. mc68hc11d0 only operates in expanded multiplexed mode and bootstrap mode. single chip special special test expanded 192 bytes static ram internal registers and i/o special modes interrupt vectors 4 kbytes rom (mc68hc11d3) boot rom $bfc0 $bfff $bf00 $bfff $7000 $7fff $0040 $00ff $0000 $003f $0000 $7000 $8000 $b000 $ffff multiplexed bootstrap external external (can be mapped to any 4-k boundary using init register) (can be mapped to any 4-k boundary using the init register) present at reset and can be disabled by rom on bit in config register. interrupt vectors are external. normal modes interrupt vectors 4-kbytes rom $ffc0 $ffff $ff00 $ffff rating symbol value unit operating temperature range mc68hc11d0c t a t l to t h ?40 to +85 c characteristic symbol value unit package thermal resistance (junction-to-ambient) 44-pin plastic leaded chip carrier (plcc) 44-pin plastic quad flat pack (qfp ja 50 85 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11d3 and mc68hc11d0 mc68hc711d3 ? rev. 2 data sheet motorola mc68hc11d3 and mc68hc11d0 141 a.6 ordering information mcu package temperature mc order number 2 mhz 3 mhz mc68hc11d3 (custom rom) 44-pin plcc ?40 to +85 c mc68hc11d3cfn2 mc68hc11d3cfn3 mc68hc11d0 (no rom) 44-pin plcc ?40 to +85 c mc68hc11d0cfn2 mc68hc11d0cfn3 44-pin qfp ?40 to +85 c mc68hc11d0cfb2 MC68HC11D0CFB3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11d3 and mc68hc11d0 data sheet mc68hc711d3 ? rev. 2 142 mc68hc11d3 and mc68hc11d0 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc711d3 ? rev. 2 data sheet motorola mc68l11d0 143 data sheet ? mc68hc711d3 appendix b. mc68l11d0 b.1 introduction the mc68l11d0 is an extended-voltage version of the mc68hc11d0 microcontroller that can operate in applications that require supply voltages as low as 3.0 volts. operation is identical to that of the mc68hc11d0 (see appendix a. mc68hc11d3 and mc68hc11d0 ) in all aspects other than electrical parameters, as shown in this appendix. features of the mc68hc11d0 include: suitable for battery-powered portable and hand-held applications excellent for use in devices such as remote sensors and actuators operating performance is same at 5 v and 3 v b.2 mc68l11d0 electri cal characteristics the parameters given in section 9. electrical characteristics apply to the mc68l11d0 with the exceptions given here. b.2.1 functional operat ing temperature range b.2.2 dc electrical characteristics rating symbol value unit operating temperature range t a t l to t h ?20 to +70 c characteristic (1) symbol min max unit output voltage (2) all outputs except xtal i load = 10.0 a all outputs except xtal, reset , and moda v ol v oh ? v dd ? 0.1 0.1 ? v output high voltage (1) all outputs except xtal, reset , and moda i load = ? 0.5 ma, v dd = 3.0 v i load = ? 0.8 ma, v dd = 4.5 v v oh v dd ? 0.8 ? v output low voltage all outputs except xtal i load = 1.6 ma, v dd = 5.0 v i load = 1.0 ma, v dd = 3.0 v v ol ? 0.4 v the dc electrical table continues on next page. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68l11d0 data sheet mc68hc711d3 ? rev. 2 144 mc68l11d0 motorola input high voltage all inputs except reset reset v ih 0.7 x v dd 0.8 x v dd v dd + 0.3 v dd + 0.3 v input low voltage all inputs v il v ss ? 0.3 0.2 x v dd v i/o ports, three-state leakage pa7, pa3, pc7?pc0, v in = v ih or v il pd7?pd0, moda/lir , reset i oz ? 10 a input leakage current v in = v dd or v ss pa 2 ? pa 0 , i r q , xirq v in = v dd or v ss modb/v stby i in ? ? 1 10 a ram standby voltage power down v sb 2.0 v dd v ram standby current power down i sb ? 10 a input capacitance pa2?pa0, irq , xirq , extal pa3, pa7, pc7?pc0, pd7?pd0, moda/lir , reset c in ? ? 8 12 pf output load capacitance all outputs except pd4?pd1 pd4?pd1 c l ? ? 90 100 pf total supply current (3) run: single-chip mode v dd = 5.5 v v dd = 3.0 v expanded multiplexed mode v dd = 5.5 v v dd = 3.0 v wait ? all peripheral functions shut down: single-chip mode v dd = 5.5 v v dd = 3.0 v expanded multiplexed mode v dd = 5.5 v v dd = 3.0 v stop ? no clocks, single-chip mode: v dd = 5.5 v v dd = 3.0 v i dd w idd s idd 8 4 14 7 3 1.5 5 2.5 50 25 15 8 27 14 6 3 10 5 50 25 ma ma a power dissipation single-chip mode v dd = 5.5 v v dd = 3.0 v expanded multiplexed mode v dd = 5.5 v v dd = 3.0 v p d 44 12 77 21 85 24 150 42 mw 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. v oh specification for reset and moda is not applicable bec ause they are open-drain pins. v oh specification is not applicable to ports c and d in wired-or mode. 3. extal is driven with a square wave, and t cyc = 1000 ns for 1 mhz rating; t cyc = 500 ns for 2 mhz rating; v il 0.2 v; v ih v dd ? 0.2 v; no dc loads characteristic (1) symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68l11d0 mc68hc711d3 ? rev. 2 data sheet motorola mc68l11d0 145 b.2.3 control timing b.2.4 peripheral port timing characteristic (1) symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation f o dc 1.0 dc 2.0 mhz e-clock period t cyc 1000 ? 500 ? ns crystal frequency f xtal ? 4.0 ? 8.0 mhz external oscillator frequency 4 f o dc 4.0 dc 8.0 mhz processor control setup time t pcsu = 1/4 t cyc + 50 ns t pcsu 325 ? 200 ? ns reset input pulse width (2) to guarantee external reset vector minimum input time can be preempted by internal reset pw rstl 8 1 ? ? 8 1 ? ? t cyc interrupt pulse width, pw irq = t cyc + 20 ns irq edge-sensitive mode pw irq 1020 ? 520 ? ns wait recovery startup time t wrs ?4?4 t cyc timer pulse width pw tim = t cyc + 20 ns input capture pulse accumulator input pw tim 1020 ? 520 ? ns 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. reset is recognized during the first clock cycle it is held lo w. internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. refer to section 4. resets, interrupts, and low-power modes for further details. characteristic (1) symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 mhz e-clock period t cyc 1000 ? 500 ? ns peripheral data setup time (2) mcu read of ports a, b, c, and d t pdsu 100 ? 100 ? ns peripheral data hold time (2) mcu read of ports a, b, c, and d t pdh 50 ? 50 ? ns delay time, peripheral data write mcu write to port a mcu writes to ports b, c, and d t pwd = 1/4 t cyc + 150 ns t pwd ? ? 200 350 ? ? 200 225 ns 1. v dd = 3.0 vd to 5.5 vdc, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. port c and d timing is valid for active drive (cwom and dwom bits not set in pioc and spcr registers respectively). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68l11d0 data sheet mc68hc711d3 ? rev. 2 146 mc68l11d0 motorola b.2.5 expansi on bus timing num characteristic (1) symbol 1.0 mhz 2.0 mhz unit min max min max frequency of operation (e-clock frequency) f o dc 1.0 dc 2.0 mhz 1 cycle time t cyc 1000 ? 500 ? ns 2 pulse width, e low, pw el = 1/2 t cyc ? 23 ns pw el 475 ? 225 ? ns 3 pulse width, e high, pw eh = 1/2 t cyc ? 28 ns pw eh 470 ? 220 ? ns 4a e and as rise time t r ?25?25ns 4b e and as fall time t f ?25?25ns 9 address hold time (2)a , t ah = 1/8 t cyc ? 29.5 ns t ah 95 ? 33 ? ns 12 non-muxed address valid time to e rise t av = pw el ? (t asd + 80 ns) (2)a t av 275 ? 88 ? ns 17 read data setup time t dsr 30 ? 30 ? ns 18 read data hold time (max = t mad )t dhr 0 150 0 88 ns 19 write data delay time, t ddw = 1/8 t cyc + 65.5 ns (2)a t ddw ? 195 ? 133 ns 21 write data hold time, t dhw = 1/8 t cyc ? 29.5 ns (2)a t dhw 95 ? 33 ? ns 22 muxed address valid time to e rise t avm = pw el ? (t asd + 90 ns) (2)a t avm 265 ? 78 ? ns 24 muxed address valid time to as fall t asl = pw ash ? 70 ns t asl 150 ? 25 ? ns 25 muxed address hold time, t ahl = 1/8 t cyc ? 29.5 ns (2)b t ahl 95 ? 33 ? ns 26 delay time, e to as rise, t asd = 1/8 t cyc ? 9.5 ns (2)a t asd 120 ? 58 ? ns 27 pulse width, as high, pw ash = 1/4 t cyc ? 29 ns pw ash 220 ? 95 ? ns 28 delay time, as to e rise, t ased = 1/8 t cyc ? 9.5 ns (2)b t ased 120 ? 58 ? ns 29 mpu address access time (2)a t acca = t cyc ? (pw el ? t avm ) ? t dsr ? t f t acca 735 ? 298 ? ns 35 mpu access time , t acce = pw eh ? t dsr t acce ? 440 ? 190 ns 36 muxed address delay (previous cycle mpu read) t mad = t asd + 30 ns (2)a t mad 150 ? 88 ? ns 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. input clocks with duty cycles other than 50% affect bus performa nce. timing parameters affect ed by input clock duty cycle are identified by (a) and (b). to recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 t cyc in the above formulas, where applicable: (a) (1-dc) 1/4 t cyc (b) dc 1/4 t cyc where: dc is the decimal va lue of duty cycle perc entage (high time). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68l11d0 mc68hc711d3 ? rev. 2 data sheet motorola mc68l11d0 147 b.2.6 serial peripheral interface timing num characteristic (1) symbol 1.0 mhz 2.0 mhz unit min max min max operating frequency master slave f op(m) f op(s) dc dc 0.5 1.0 dc dc 0.5 2.0 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 1000 ? ? 2.0 500 ? ? t cyc ns 2 enable lead time master (2) slave t lead(m) t lead(s) ? 500 ? ? ? 250 ? ? ns 3 enable lag time master (2) slave t lag(m) t lag(s) ? 500 ? ? ? 250 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 680 380 ? ? 340 190 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 680 380 ? ? 340 190 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? 100 100 ? ? ns 8 access time (time to data ac tive from high-impedance state) slave t a 0 120 0 120 ns 9 disable time (hold time to high-impedance state) slave t dis ? 240 ? 240 ns 10 data valid (after enable edge) (3) t v(s) ? 240 ? 240 ns 11 data hold time (outputs) (after enable edge) t ho 0?0?ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 100 2.0 ? ? 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 100 2.0 ? ? 100 2.0 ns s 1. v dd = 3.0 vdc to 5.5 vdc, v ss = 0 vdc, t a = t l to t h . all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. signal production depends on software. 3. assumes 100 pf load on all spi pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68l11d0 data sheet mc68hc711d3 ? rev. 2 148 mc68l11d0 motorola b.3 ordering information package frequency features mc order number 44-pin plcc 2 mhz no rom mc68l11d0fn2 44-pin qfp 2 mhz no rom mc68l11d0fb2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68hc711d3/d rev. 2 9/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any pro duct or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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